  # 56001 Digital Signal Processor

  DSP main page,
  DSP System calls.
  DMA System calls.
  DSP Host Communication Example.
  DMA Handshaked Communication Example.

  # Typical DSP Applications

  - Fast Fourier Transform (FFT)
  - Scalar, Vector, and Matrix Arithmetic
  - Music Processing (MPEG audio, AC-3, Digital Audio Broadcasting)
  - Vector Graphics
  - Noise Cancelation
  - Encryption/Scrambling
  - Finite Impulse Response (FIR) Filter
  - Speech Sythesizer/Recognizer
  - Image Compression
  - Optical Character Recognition (OCR)

  # Architectural Overview

  The A T A R I Falcon features a 32MHz 56001 Digital Signal Processor with 96k byte zero wait-state SRAM. There are three independent memory spaces, X data, Y data and program memory. The lowest 512 locations are on-chip internal SRAM (0-512). The external SRAM is divided into two separate 16k word blocks of X and Y data spaces ($0200-$3fff). External program memory physically overlaps both X and Y external data spaces. Data paths are 24 bits wide.

  # Instruction Example

  The number of clock cycles per instruction is typically 2, allowing most instructions to run at 16 MIPS. Many instructions also feature parallel moves, which means moving data in parallel with the instruction.

  >     macr x0,y0,B   B,x1  Y:(r4)+n4,y1

  The macr instruction multiplies the signed 24-bits value in the x0 register by the signed 24-bits value in the y0 register, adds the resulting product to the 56-bit B accumulator and then rounds the result into the B1 portion of the accumulator. In parallel, the old value in B1 is stored in the in 24-bits x1 register and a 24-bits value is fetched from the Y data space with the address in the 16-bits r4 register and stored in the 24-bits y1 register. The r4 register is postincremented by the value in the 16-bits n4 register.