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The files enclosed are GAL programs used by my modified Hypercache+ Board.

GALs A-C correspond roughly to the original circuits and are installed in
the same sockets, but many of their pins are rewired for altered functions.
This is especially true of GAL B which has been changed from a GAL20V8 to
a GAL16V8 to achieve higher signal speed.

The main cache RAMs, as well as the cache tag RAMs are identical to the
original ones, and are identically connected except that some signals
now connect to different GAL pins (as mentioned above).

I never did make a full schematic of of the altered board, but if you
have an original board, it should be possible to puzzle out how the
changes were implemented from the GAL logic equations. (*.LCI & *.LOG).

The GAL called PLL_32 is a Phase Locked Loop 32 & 8 MHz Generator,
which I implemented as an an add on board mounted piggyback in the
sockets that were originally intended for clock generation (at edge).
This board also held a VCO centred at 32 MHz and the mandatory PLL
feedback low-pass filter.

I hope you can make sense of this stuff, despite the lack of 'proper'
documentation.

Ronald Andersson.
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Internet mailto: dlanor@oden.se

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