### Equations

********** Mapped Logic **********
$OpTx$BIN_STEP$760 <= ((NOT a(1) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT a(2) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR ( use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (a(14) AND a(15) AND NOT a(12) AND NOT oldos_n) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
$OpTx$FX_DC$499 <= (NOT a(6) AND NOT a(5) AND a(4));
$OpTx$FX_DC$508 <= (NOT a(6) AND NOT a(5) AND NOT a(4));
$OpTx$FX_DC$510 <= ((use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
$OpTx$FX_DC$521 <= (a(14) AND a(15) AND NOT a(11) AND NOT a(13) AND NOT a(7) AND a(12));
$OpTx$FX_DC$522 <= (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(1));
$OpTx$FX_DC$538 <= ((merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(13) AND NOT a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2));
$OpTx$FX_DC$540 <= ((use_cartemu/cfg_sram_bank(5) AND use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_bank(5) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/usdx_bank(5) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
$OpTx$FX_DC$571 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(1) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(1) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
$OpTx$FX_DC$577 <= ((use_cartemu/cfg_menu) OR (use_cartemu/cfg_bank(6) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_usdx(0) AND use_cartemu/cfg_usdx(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
$OpTx$FX_DC$580 <= (a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(4) AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2);
$OpTx$FX_DC$601 <= ((use_cartemu/cfg_mode(1)) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1)));
$OpTx$FX_DC$608 <= ((use_cartemu/cfg_sram_bank(0) AND use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/usdx_bank(0) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND use_cartemu/N29/use_cartemu/N29_D2));
$OpTx$FX_SC$586 <= (a(9) AND a(8) AND a(10) AND a(7));
$OpTx$FX_SC$591 <= (a(14) AND a(15) AND NOT rw AND NOT a(11) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2));
$OpTx$INV$490 <= ((use_cartemu/cfg_menu) OR (NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_usdx(0) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_usdx(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_source_ram AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
N0/N0_TRST <= ((freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND use_freezer/state(2)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$BIN_STEP$760));
FDCPE_activate_n_sync0: FDCPE port map (activate_n_sync(0),activate_n_in,NOT phi2,'0','0');
FDCPE_activate_n_sync1: FDCPE port map (activate_n_sync(1),activate_n_sync(0),NOT phi2,'0','0');
d_I(0) <= ((rw AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N50/use_cartemu/N50_D2) OR (use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT use_freezer/state(1) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2)); d(0) <= d_I(0) when d_OE(0) = '1' else 'Z'; d_OE(0) <= dout_enable;
d_I(1) <= ((rw AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND a(1) AND use_cartemu/cfg_usdx(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_source_ram AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (rw AND a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_sram_bank(1) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(1) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499)); d(1) <= d_I(1) when d_OE(1) = '1' else 'Z'; d_OE(1) <= dout_enable;
d_I(2) <= ((rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(2) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (rw AND use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_sram_bank(2) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499)); d(2) <= d_I(2) when d_OE(2) = '1' else 'Z'; d_OE(2) <= dout_enable;
d_I(3) <= ((rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(3) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(3) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(3) <= d_I(3) when d_OE(3) = '1' else 'Z'; d_OE(3) <= dout_enable;
d_I(4) <= ((rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(4) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(4) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(4) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(4) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(4) <= d_I(4) when d_OE(4) = '1' else 'Z'; d_OE(4) <= dout_enable;
d_I(5) <= ((rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(5) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(5) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(5) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(5) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(5) <= d_I(5) when d_OE(5) = '1' else 'Z'; d_OE(5) <= dout_enable;
d_I(6) <= ((rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_ctl(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_ctl(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(6) <= d_I(6) when d_OE(6) = '1' else 'Z'; d_OE(6) <= dout_enable;
d_I(7) <= (rw AND use_cartemu/usdx_ctl(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2); d(7) <= d_I(7) when d_OE(7) = '1' else 'Z'; d_OE(7) <= dout_enable;
dout_enable <= ((rw AND a(6) AND a(5) AND phi2 AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND phi2 AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND phi2 AND use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND phi2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND NOT a(1) AND a(4) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND NOT a(2) AND a(4) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2));
freezer_mem_dout(5)/freezer_mem_dout(5)_D2 <= ((a(14) AND a(15) AND rw AND a(11) AND a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND a(13) AND a(4) AND a(7) AND a(3) AND a(0) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND rw AND a(11) AND a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND a(13) AND a(4) AND a(7) AND a(3) AND a(0) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2) AND use_freezer/state(0)));
merged_out_dout_or0000/merged_out_dout_or0000_D2 <= ((freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND NOT rw AND NOT a(11) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND use_freezer/state(2)));
FTCPE_powerup_n: FTCPE port map (powerup_n,'1',NOT phi2,'0','0',powerup_n_CE); powerup_n_CE <= (NOT powerup_n AND reset_n_sync(2) AND NOT reset_n_sync(3));
ram0_ce <= NOT (((phi2 AND oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(14) AND NOT a(15) AND phi2 AND NOT a(13) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND NOT a(15) AND phi2 AND NOT a(13) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (a(14) AND a(15) AND NOT rw AND NOT a(11) AND phi2 AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(15) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2)));
ram1_ce <= NOT (((phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$577) OR (a(14) AND a(15) AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2)));
ram_a(4) <= ((a(14) AND a(15) AND a(13) AND a(4) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(9) AND NOT a(8) AND NOT a(10) AND a(4) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(8) AND NOT a(10) AND a(4) AND NOT dualpokey_n AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (a(4) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(4) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND a(4) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(4) AND NOT use_freezer/use_status_as_ram_address(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/use_status_as_ram_address(0) AND use_freezer/vector_a2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2));
ram_a(5) <= ((a(14) AND a(15) AND a(5) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (a(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(5) AND a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/use_status_as_ram_address(0) AND NOT dualpokey_n AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2));
ram_a(6) <= ((a(6) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND a(6) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2));
ram_a(7) <= ((a(7) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND a(13) AND a(7) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2));
ram_rom_a(12) <= ((a(13) AND a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND NOT a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_0 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1) AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(14) AND a(15) AND a(13) AND a(12) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/oss_bank(0) AND NOT a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT use_cartemu/cfg_mode(0) AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (use_cartemu/cfg_menu AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2));
ram_rom_a(13) <= (($OpTx$FX_DC$538) OR (a(13) AND use_freezer/rom_bank_0 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_1 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_cartemu/cfg_menu AND use_cartemu/cfg_bank(0) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND use_cartemu/N29/use_cartemu/N29_D2) OR (NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/oss_bank(1) AND NOT a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT use_cartemu/cfg_menu AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$608));
ram_rom_a(14) <= (($OpTx$FX_DC$538) OR (use_pia/pia_portb(2) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND use_freezer/rom_bank_1 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(2) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$571));
ram_rom_a(15) <= (($OpTx$FX_DC$538) OR (a(13) AND use_freezer/rom_bank_2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(3) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(3) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2) OR (NOT a(13) AND use_freezer/ram_bank_3 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2));
ram_rom_a(16) <= (($OpTx$FX_DC$538) OR (use_pia/pia_portb(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND use_freezer/rom_bank_3 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_4 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2));
ram_rom_a(17) <= ((use_freezer/rom_bank_4 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2));
ram_rom_a(18) <= ((NOT a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (use_freezer/rom_bank_5 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (use_cartemu/cfg_menu AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (NOT use_pia/pia_ddrb(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$540));
ram_rom_oe <= NOT ((rw AND phi2));
ram_rom_we <= NOT ((NOT rw AND phi2short));
ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2 <= (a(14) AND NOT ramdisk_enable_n AND NOT a(15) AND use_pia/pia_ddrb(4) AND NOT use_pia/pia_portb(4));
refresh_I <= '0'; refresh <= refresh_I when refresh_OE = '1' else 'Z'; refresh_OE <= N0/N0_TRST;
FDCPE_reset_n_sync0: FDCPE port map (reset_n_sync(0),reset_n_in,NOT phi2,'0','0');
FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync(1),reset_n_sync(0),NOT phi2,'0','0');
FDCPE_reset_n_sync2: FDCPE port map (reset_n_sync(2),reset_n_sync(1),NOT phi2,'0','0');
FDCPE_reset_n_sync3: FDCPE port map (reset_n_sync(3),reset_n_sync(2),NOT phi2,'0','0');
rom0_ce <= NOT (((NOT a(15) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(14) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2)));
rom1_ce <= NOT (((a(14) AND a(15) AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (phi2 AND a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$577) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND rw AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)));
use_cartemu/N29/use_cartemu/N29_D2 <= (( NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1)) OR (NOT $OpTx$FX_DC$522 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
use_cartemu/N4/use_cartemu/N4_D2 <= (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(13) AND use_cartemu/cfg_sram_enable AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2);
use_cartemu/N50/use_cartemu/N50_D2 <= ((NOT a(6) AND NOT a(5) AND a(1) AND use_cartemu/cfg_usdx(0) AND a(2) AND a(4) AND NOT a(0)) OR (NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND use_cartemu/cfg_sram_bank(0) AND NOT a(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND NOT a(0) AND use_cartemu/usdx_bank(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND NOT a(0) AND use_cartemu/usdx_bank(0)) OR (NOT a(6) AND NOT a(5) AND use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(4) AND NOT a(0)) OR (NOT a(6) AND NOT a(5) AND a(1) AND use_cartemu/cfg_sram_enable AND NOT a(2) AND a(4) AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(4) AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND a(2) AND a(4) AND use_cartemu/cfg_write_enable AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(0) AND a(4) AND NOT a(0)));
use_cartemu/N97/use_cartemu/N97_D2 <= ((a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0)));
use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 <= ((NOT use_cartemu/cfg_usdx(0) AND NOT use_cartemu/cfg_usdx(1)) OR (NOT use_cartemu/usdx_ctl(0) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2));
use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(2) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(2) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(2) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(3) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(3) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(3) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(4) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(4) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(4) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2));
use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 <= ((use_cartemu/cfg_usdx(0) AND NOT use_cartemu/usdx_ctl(1)) OR (use_cartemu/cfg_usdx(1) AND NOT use_cartemu/usdx_ctl(1)));
use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 <= ((NOT a(14) AND a(15) AND use_cartemu/cfg_enable AND a(13) AND NOT use_cartemu/N29/use_cartemu/N29_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/cfg_enable AND NOT use_cartemu/N29/use_cartemu/N29_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_enable AND a(13) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cfg_enable AND a(13) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (NOT use_cartemu/cfg_menu AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT a(14) AND a(15) AND use_cartemu/cfg_menu AND a(13)) OR (NOT a(14) AND a(15) AND a(13) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2));
use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 <= ((a(14) AND a(15) AND NOT a(11) AND NOT a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT flash_we_n) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT cartemu_enable_n));
FDCPE_use_cartemu/cfg_bank0: FDCPE port map (use_cartemu/cfg_bank(0),use_cartemu/cfg_bank_D(0),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(0) <= ((NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (use_cartemu/cfg_bank(0) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2));
FDCPE_use_cartemu/cfg_bank1: FDCPE port map (use_cartemu/cfg_bank(1),use_cartemu/cfg_bank_D(1),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(1) <= ((use_cartemu/cfg_bank(1) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FDCPE_use_cartemu/cfg_bank2: FDCPE port map (use_cartemu/cfg_bank(2),use_cartemu/cfg_bank_D(2),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(2) <= ((a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(2) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (use_cartemu/cfg_bank(2) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(2) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2));
FDCPE_use_cartemu/cfg_bank3: FDCPE port map (use_cartemu/cfg_bank(3),use_cartemu/cfg_bank_D(3),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(3) <= ((use_cartemu/cfg_bank(3) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(3).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FDCPE_use_cartemu/cfg_bank4: FDCPE port map (use_cartemu/cfg_bank(4),use_cartemu/cfg_bank_D(4),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(4) <= ((use_cartemu/cfg_bank(4) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(4) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(4) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(4).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FDCPE_use_cartemu/cfg_bank5: FDCPE port map (use_cartemu/cfg_bank(5),use_cartemu/cfg_bank_D(5),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(5) <= ((use_cartemu/cfg_bank(5) AND NOT $OpTx$FX_DC$510) OR (a(5) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND a(5) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(5).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_bank6: FTCPE port map (use_cartemu/cfg_bank(6),use_cartemu/cfg_bank_T(6),NOT phi2short,'0','0'); use_cartemu/cfg_bank_T(6) <= ((a(6) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND NOT use_cartemu/cfg_bank(6) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT a(6) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cfg_bank(6) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND NOT d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND NOT use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_enable: FTCPE port map (use_cartemu/cfg_enable,use_cartemu/cfg_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_enable_T <= ((use_cartemu/cfg_write_enable.EXP) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT rw AND use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (use_cartemu/cfg_enable AND NOT powerup_n AND NOT reset_n_sync(1)) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT use_cartemu/cfg_enable AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cfg_enable AND a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508));
FTCPE_use_cartemu/cfg_menu: FTCPE port map (use_cartemu/cfg_menu,use_cartemu/cfg_menu_T,NOT phi2short,'0','0'); use_cartemu/cfg_menu_T <= ((use_cartemu/cfg_menu AND NOT powerup_n AND NOT reset_n_sync(1) AND cartemu_enable_n) OR (NOT use_cartemu/cfg_menu AND NOT powerup_n AND NOT reset_n_sync(1) AND NOT cartemu_enable_n) OR (NOT rw AND use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND NOT d(2).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_mode0: FTCPE port map (use_cartemu/cfg_mode(0),use_cartemu/cfg_mode_T(0),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(0) <= ((use_cartemu/cfg_mode(0) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_mode1: FTCPE port map (use_cartemu/cfg_mode(1),use_cartemu/cfg_mode_T(1),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(1) <= ((use_cartemu/cfg_mode(1) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_mode2: FTCPE port map (use_cartemu/cfg_mode(2),use_cartemu/cfg_mode_T(2),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(2) <= ((use_cartemu/cfg_mode(2) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_source_ram: FTCPE port map (use_cartemu/cfg_source_ram,use_cartemu/cfg_source_ram_T,NOT phi2short,'0','0'); use_cartemu/cfg_source_ram_T <= ((NOT powerup_n AND use_cartemu/cfg_source_ram AND NOT reset_n_sync(1)) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_source_ram AND NOT d(1).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND NOT use_cartemu/cfg_source_ram AND d(1).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FDCPE_use_cartemu/cfg_sram_bank0: FDCPE port map (use_cartemu/cfg_sram_bank(0),use_cartemu/cfg_sram_bank_D(0),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(0) <= ((d(0).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(0) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FDCPE_use_cartemu/cfg_sram_bank1: FDCPE port map (use_cartemu/cfg_sram_bank(1),use_cartemu/cfg_sram_bank_D(1),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(1) <= ((d(1).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(1) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FDCPE_use_cartemu/cfg_sram_bank2: FDCPE port map (use_cartemu/cfg_sram_bank(2),use_cartemu/cfg_sram_bank_D(2),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(2) <= ((d(2).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(2) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FDCPE_use_cartemu/cfg_sram_bank3: FDCPE port map (use_cartemu/cfg_sram_bank(3),use_cartemu/cfg_sram_bank_D(3),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(3) <= ((d(3).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(3) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FDCPE_use_cartemu/cfg_sram_bank4: FDCPE port map (use_cartemu/cfg_sram_bank(4),use_cartemu/cfg_sram_bank_D(4),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(4) <= ((d(4).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(4) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FDCPE_use_cartemu/cfg_sram_bank5: FDCPE port map (use_cartemu/cfg_sram_bank(5),use_cartemu/cfg_sram_bank_D(5),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(5) <= ((d(5).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(5) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 <= (NOT rw AND a(1) AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499);
FTCPE_use_cartemu/cfg_sram_enable: FTCPE port map (use_cartemu/cfg_sram_enable,use_cartemu/cfg_sram_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_sram_enable_T <= ((use_cartemu/cfg_sram_enable AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499));
FTCPE_use_cartemu/cfg_usdx0: FTCPE port map (use_cartemu/cfg_usdx(0),use_cartemu/cfg_usdx_T(0),NOT phi2short,'0','0'); use_cartemu/cfg_usdx_T(0) <= ((use_cartemu/cfg_usdx(0) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_usdx(0) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_usdx(0) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FTCPE_use_cartemu/cfg_usdx1: FTCPE port map (use_cartemu/cfg_usdx(1),use_cartemu/cfg_usdx_T(1),NOT phi2short,'0','0'); use_cartemu/cfg_usdx_T(1) <= ((use_cartemu/cfg_usdx(1) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_usdx(1) AND a(7) AND NOT d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_usdx(1) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2));
FTCPE_use_cartemu/cfg_write_enable: FTCPE port map (use_cartemu/cfg_write_enable,use_cartemu/cfg_write_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_write_enable_T <= ((NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND d(0).PIN AND NOT use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (use_cartemu/cfg_write_enable AND NOT reset_n_sync(1)) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_write_enable AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508));
use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 <= (( NOT use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2) OR (NOT rw AND use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT $OpTx$INV$490 AND NOT use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 AND NOT use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 AND NOT $OpTx$FX_DC$571 AND NOT use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 AND $OpTx$FX_DC$540) OR (NOT rw AND use_cartemu/cfg_menu) OR (NOT $OpTx$INV$490 AND $OpTx$FX_DC$577) OR (NOT rw AND NOT use_cartemu/cfg_write_enable AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT rw AND flash_we_n AND NOT use_cartemu/N4/use_cartemu/N4_D2));
FTCPE_use_cartemu/oss_bank0: FTCPE port map (use_cartemu/oss_bank(0),use_cartemu/oss_bank_T(0),NOT phi2short,'0','0'); use_cartemu/oss_bank_T(0) <= ((use_cartemu/cfg_mode(0) AND NOT a(7) AND a(3) AND use_cartemu/oss_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522) OR (use_cartemu/cfg_mode(0) AND NOT a(7) AND NOT a(3) AND NOT use_cartemu/oss_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522));
FTCPE_use_cartemu/oss_bank1: FTCPE port map (use_cartemu/oss_bank(1),use_cartemu/oss_bank_T(1),NOT phi2short,'0','0'); use_cartemu/oss_bank_T(1) <= ((use_cartemu/cfg_mode(0) AND NOT a(7) AND a(0) AND NOT use_cartemu/oss_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522) OR (use_cartemu/cfg_mode(0) AND NOT a(7) AND NOT a(0) AND use_cartemu/oss_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522));
use_cartemu/trig3_disable_atari <= ((rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_menu AND a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_mode(0) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521 AND NOT $OpTx$FX_DC$601) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521));
FTCPE_use_cartemu/usdx_bank0: FTCPE port map (use_cartemu/usdx_bank(0),use_cartemu/usdx_bank_T(0),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(0) <= ((NOT rw AND d(0).PIN AND NOT use_cartemu/usdx_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(0).PIN AND use_cartemu/usdx_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_bank1: FTCPE port map (use_cartemu/usdx_bank(1),use_cartemu/usdx_bank_T(1),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(1) <= ((NOT rw AND d(1).PIN AND NOT use_cartemu/usdx_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(1).PIN AND use_cartemu/usdx_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_bank2: FTCPE port map (use_cartemu/usdx_bank(2),use_cartemu/usdx_bank_T(2),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(2) <= ((NOT rw AND d(2).PIN AND NOT use_cartemu/usdx_bank(2) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(2).PIN AND use_cartemu/usdx_bank(2) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_bank3: FTCPE port map (use_cartemu/usdx_bank(3),use_cartemu/usdx_bank_T(3),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(3) <= ((NOT rw AND d(3).PIN AND NOT use_cartemu/usdx_bank(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(3).PIN AND use_cartemu/usdx_bank(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_bank4: FTCPE port map (use_cartemu/usdx_bank(4),use_cartemu/usdx_bank_T(4),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(4) <= ((NOT rw AND d(4).PIN AND NOT use_cartemu/usdx_bank(4) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(4).PIN AND use_cartemu/usdx_bank(4) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_bank5: FTCPE port map (use_cartemu/usdx_bank(5),use_cartemu/usdx_bank_T(5),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(5) <= ((NOT rw AND d(5).PIN AND NOT use_cartemu/usdx_bank(5) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(5).PIN AND use_cartemu/usdx_bank(5) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_ctl0: FTCPE port map (use_cartemu/usdx_ctl(0),use_cartemu/usdx_ctl_T(0),NOT phi2short,'0','0'); use_cartemu/usdx_ctl_T(0) <= ((NOT powerup_n AND use_cartemu/usdx_ctl(0) AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/usdx_ctl(0) AND reset_n_sync(1) AND NOT d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT use_cartemu/usdx_ctl(0) AND reset_n_sync(1) AND d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
FTCPE_use_cartemu/usdx_ctl1: FTCPE port map (use_cartemu/usdx_ctl(1),use_cartemu/usdx_ctl_T(1),NOT phi2short,'0','0'); use_cartemu/usdx_ctl_T(1) <= ((NOT powerup_n AND NOT use_cartemu/usdx_ctl(1) AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/usdx_ctl(1) AND reset_n_sync(1) AND NOT d(7).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT use_cartemu/usdx_ctl(1) AND reset_n_sync(1) AND d(7).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2));
use_freezer/N24/use_freezer/N24_D2 <= ((NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0)));
FDCPE_use_freezer/next_state_FSM_FFd1: FDCPE port map (use_freezer/next_state_FSM_FFd1,use_freezer/next_state_FSM_FFd1_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd1_D <= ((NOT rw AND reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1) OR (reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (reset_n_sync(1) AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$580));
FDCPE_use_freezer/next_state_FSM_FFd2: FDCPE port map (use_freezer/next_state_FSM_FFd2,use_freezer/next_state_FSM_FFd2_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd2_D <= ((reset_n_sync(1) AND use_freezer/next_state_FSM_FFd2 AND NOT $OpTx$FX_DC$580) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd3 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586));
FDCPE_use_freezer/next_state_FSM_FFd3: FDCPE port map (use_freezer/next_state_FSM_FFd3,use_freezer/next_state_FSM_FFd3_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd3_D <= ((reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (NOT rw AND reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND NOT a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586));
use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 <= (a(9) AND a(8) AND a(10) AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521);
FTCPE_use_freezer/ram_bank_0: FTCPE port map (use_freezer/ram_bank_0,use_freezer/ram_bank_0_T,NOT phi2short,'0','0'); use_freezer/ram_bank_0_T <= ((use_freezer/ram_bank_0 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(0) AND a(12) AND use_freezer/ram_bank_0 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586));
FTCPE_use_freezer/ram_bank_1: FTCPE port map (use_freezer/ram_bank_1,use_freezer/ram_bank_1_T,NOT phi2short,'0','0'); use_freezer/ram_bank_1_T <= ((use_freezer/ram_bank_1 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(13) AND a(12) AND use_freezer/ram_bank_1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586));
FTCPE_use_freezer/ram_bank_2: FTCPE port map (use_freezer/ram_bank_2,use_freezer/ram_bank_2_T,NOT phi2short,'0','0'); use_freezer/ram_bank_2_T <= ((use_freezer/ram_bank_2 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(2) AND a(12) AND use_freezer/ram_bank_2 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586));
FTCPE_use_freezer/ram_bank_3: FTCPE port map (use_freezer/ram_bank_3,use_freezer/ram_bank_3_T,NOT phi2short,'0','0'); use_freezer/ram_bank_3_T <= ((use_freezer/ram_bank_3 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(3) AND a(12) AND use_freezer/ram_bank_3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586));
FTCPE_use_freezer/ram_bank_4: FTCPE port map (use_freezer/ram_bank_4,use_freezer/ram_bank_4_T,NOT phi2short,'0','0'); use_freezer/ram_bank_4_T <= ((use_freezer/ram_bank_4 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(4) AND a(12) AND use_freezer/ram_bank_4 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586));
FTCPE_use_freezer/rom_bank_0: FTCPE port map (use_freezer/rom_bank_0,use_freezer/rom_bank_0_T,NOT phi2short,'0','0'); use_freezer/rom_bank_0_T <= ((use_freezer/rom_bank_0 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(0) AND use_freezer/rom_bank_0 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FTCPE_use_freezer/rom_bank_1: FTCPE port map (use_freezer/rom_bank_1,use_freezer/rom_bank_1_T,NOT phi2short,'0','0'); use_freezer/rom_bank_1_T <= ((use_freezer/rom_bank_1 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(1) AND use_freezer/rom_bank_1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FTCPE_use_freezer/rom_bank_2: FTCPE port map (use_freezer/rom_bank_2,use_freezer/rom_bank_2_T,NOT phi2short,'0','0'); use_freezer/rom_bank_2_T <= ((NOT use_freezer/rom_bank_2 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(2) AND NOT use_freezer/rom_bank_2 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FTCPE_use_freezer/rom_bank_3: FTCPE port map (use_freezer/rom_bank_3,use_freezer/rom_bank_3_T,NOT phi2short,'0','0'); use_freezer/rom_bank_3_T <= ((NOT use_freezer/rom_bank_3 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(3) AND NOT use_freezer/rom_bank_3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FTCPE_use_freezer/rom_bank_4: FTCPE port map (use_freezer/rom_bank_4,use_freezer/rom_bank_4_T,NOT phi2short,'0','0'); use_freezer/rom_bank_4_T <= ((NOT use_freezer/rom_bank_4 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(4) AND NOT use_freezer/rom_bank_4 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FTCPE_use_freezer/rom_bank_5: FTCPE port map (use_freezer/rom_bank_5,use_freezer/rom_bank_5_T,NOT phi2short,'0','0'); use_freezer/rom_bank_5_T <= ((NOT use_freezer/rom_bank_5 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND NOT use_freezer/rom_bank_5 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521));
FDCPE_use_freezer/state0: FDCPE port map (use_freezer/state(0),use_freezer/next_state_FSM_FFd3,NOT phi2,'0','0');
FDCPE_use_freezer/state1: FDCPE port map (use_freezer/state(1),use_freezer/next_state_FSM_FFd2,NOT phi2,'0','0');
FDCPE_use_freezer/state2: FDCPE port map (use_freezer/state(2),use_freezer/next_state_FSM_FFd1,NOT phi2,'0','0');
FTCPE_use_freezer/use_status_as_ram_address0: FTCPE port map (use_freezer/use_status_as_ram_address(0),use_freezer/use_status_as_ram_address_T(0),NOT phi2short,'0','0'); use_freezer/use_status_as_ram_address_T(0) <= ((use_freezer/use_status_as_ram_address(0) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (NOT rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND use_freezer/use_status_as_ram_address(0) AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2));
FDCPE_use_freezer/vector_a2: FDCPE port map (use_freezer/vector_a2,a(2),NOT phi2short,'0','0',use_freezer/vector_a2_CE); use_freezer/vector_a2_CE <= (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND NOT a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586);
FTCPE_use_pia/pia_crb2: FTCPE port map (use_pia/pia_crb2,use_pia/pia_crb2_T,NOT phi2short,'0','0'); use_pia/pia_crb2_T <= ((use_pia/pia_crb2 AND NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND a(1) AND NOT a(2) AND NOT d(2).PIN AND NOT a(3) AND a(0) AND use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (NOT rw AND a(9) AND a(8) AND a(1) AND NOT a(2) AND d(2).PIN AND NOT a(3) AND a(0) AND NOT use_pia/pia_crb2 AND reset_n_sync(1) AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2));
FDCPE_use_pia/pia_ddrb2: FDCPE port map (use_pia/pia_ddrb(2),use_pia/pia_ddrb_D(2),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(2) <= ((use_pia/pia_ddrb(2) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(2).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
FDCPE_use_pia/pia_ddrb3: FDCPE port map (use_pia/pia_ddrb(3),use_pia/pia_ddrb_D(3),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(3) <= ((use_pia/pia_ddrb(3) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(3).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
FDCPE_use_pia/pia_ddrb4: FDCPE port map (use_pia/pia_ddrb(4),use_pia/pia_ddrb_D(4),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(4) <= ((use_pia/pia_ddrb(4) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(4).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
FDCPE_use_pia/pia_ddrb5: FDCPE port map (use_pia/pia_ddrb(5),use_pia/pia_ddrb_D(5),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(5) <= ((use_pia/pia_ddrb(5) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(5).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
FDCPE_use_pia/pia_ddrb6: FDCPE port map (use_pia/pia_ddrb(6),use_pia/pia_ddrb_D(6),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(6) <= ((use_pia/pia_ddrb(6) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (reset_n_sync(1) AND d(6).PIN AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
FDCPE_use_pia/pia_ddrb7: FDCPE port map (use_pia/pia_ddrb(7),use_pia/pia_ddrb_D(7),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(7) <= ((use_pia/pia_ddrb(7) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (reset_n_sync(1) AND d(7).PIN AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2));
use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 <= ((NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND NOT a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND NOT use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2));
FDCPE_use_pia/pia_portb2: FDCPE port map (use_pia/pia_portb(2),use_pia/pia_portb_D(2),NOT phi2short,'0','0'); use_pia/pia_portb_D(2) <= ((use_pia/pia_portb(2) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(2).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
FDCPE_use_pia/pia_portb3: FDCPE port map (use_pia/pia_portb(3),use_pia/pia_portb_D(3),NOT phi2short,'0','0'); use_pia/pia_portb_D(3) <= ((use_pia/pia_portb(3) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(3).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
FDCPE_use_pia/pia_portb4: FDCPE port map (use_pia/pia_portb(4),use_pia/pia_portb_D(4),NOT phi2short,'0','0'); use_pia/pia_portb_D(4) <= ((use_pia/pia_portb(4) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(4).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
FDCPE_use_pia/pia_portb5: FDCPE port map (use_pia/pia_portb(5),use_pia/pia_portb_D(5),NOT phi2short,'0','0'); use_pia/pia_portb_D(5) <= ((use_pia/pia_portb(5) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(5).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
FDCPE_use_pia/pia_portb6: FDCPE port map (use_pia/pia_portb(6),use_pia/pia_portb_D(6),NOT phi2short,'0','0'); use_pia/pia_portb_D(6) <= ((use_pia/pia_portb(6) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (reset_n_sync(1) AND d(6).PIN AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
FDCPE_use_pia/pia_portb7: FDCPE port map (use_pia/pia_portb(7),use_pia/pia_portb_D(7),NOT phi2short,'0','0'); use_pia/pia_portb_D(7) <= ((use_pia/pia_portb(7) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (reset_n_sync(1) AND d(7).PIN AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2));
use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 <= ((NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND NOT a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);