Release 12.4 - xst M.81d (lin64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Reading design: TurboFreezer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "TurboFreezer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "TurboFreezer"
Output Format                      : NGC
Target Device                      : XC9500XL CPLDs

---- Source Options
Top Module Name                    : TurboFreezer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : User
Safe Implementation                : No
Mux Extraction                     : Yes
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 2
Keep Hierarchy                     : Yes
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Verilog 2001                       : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================

Setting FSM Encoding Algorithm to : User


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/FreezerDef.vhd" in Library work.
Package <FreezerDef> compiled.
Package body <FreezerDef> compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/FreezerLogic.vhd" in Library work.
Entity <FreezerLogic> compiled.
Entity <FreezerLogic> (Architecture <RTL>) compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/CartEmu.vhd" in Library work.
Entity <CartEmu> compiled.
Entity <CartEmu> (Architecture <RTL>) compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/OldOs.vhd" in Library work.
Entity <OldOs> compiled.
Entity <OldOs> (Architecture <RTL>) compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/PIA.vhd" in Library work.
Entity <PIA> compiled.
Entity <PIA> (Architecture <RTL>) compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/Ramdisk.vhd" in Library work.
Entity <Ramdisk> compiled.
Entity <Ramdisk> (Architecture <RTL>) compiled.
Compiling vhdl file "/home/hias/private/xl/turbo-freezer/xilinx/svn/TurboFreezer.vhd" in Library work.
Entity <TurboFreezer> compiled.
Entity <TurboFreezer> (Architecture <RTL>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <TurboFreezer> in library <work> (architecture <RTL>).

Analyzing hierarchy for entity <FreezerLogic> in library <work> (architecture <RTL>).

Analyzing hierarchy for entity <CartEmu> in library <work> (architecture <RTL>).

Analyzing hierarchy for entity <OldOs> in library <work> (architecture <RTL>).

Analyzing hierarchy for entity <PIA> in library <work> (architecture <RTL>).

Analyzing hierarchy for entity <Ramdisk> in library <work> (architecture <RTL>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <TurboFreezer> in library <work> (Architecture <RTL>).
    Set user-defined property "SLOW =  TRUE" for unit <TurboFreezer>.
    Set user-defined property "LOC =  P15 P14 P13 P12 P11 P10 P9 P8 P6 P4 P3 P1 P36 P35 P50 P42" for signal <a> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P30 P29 P28 P25 P20 P18 P17 P16" for signal <d> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P33" for signal <rw> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P95 P94 P93 P92" for signal <ram_a> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P91 P90 P89 P87 P86 P85 P82" for signal <ram_rom_a> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P78" for signal <ram_rom_oe> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P77" for signal <ram_rom_we> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P81" for signal <ram0_ce> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P96" for signal <ram1_ce> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P79" for signal <rom0_ce> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P97" for signal <rom1_ce> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P73" for signal <refresh> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P22" for signal <phi2> in unit <TurboFreezer>.
    Set user-defined property "BUFG =  clk" for signal <phi2> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P27" for signal <phi2short> in unit <TurboFreezer>.
    Set user-defined property "BUFG =  clk" for signal <phi2short> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P46" for signal <activate_n_in> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P43" for signal <oldos_n> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P19" for signal <flash_we_n> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P7" for signal <cartemu_enable_n> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P24" for signal <ramdisk_enable_n> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P34" for signal <dualpokey_n> in unit <TurboFreezer>.
    Set user-defined property "LOC =  P99" for signal <reset_n_in> in unit <TurboFreezer>.
    Set user-defined property "NOREDUCE =  true" for signal <dout_enable>.
Entity <TurboFreezer> analyzed. Unit <TurboFreezer> generated.

Analyzing Entity <FreezerLogic> in library <work> (Architecture <RTL>).
Entity <FreezerLogic> analyzed. Unit <FreezerLogic> generated.

Analyzing Entity <CartEmu> in library <work> (Architecture <RTL>).
    Set user-defined property "KEEP =  TRUE" for signal <trig3_disable_atari>.
Entity <CartEmu> analyzed. Unit <CartEmu> generated.

Analyzing Entity <OldOs> in library <work> (Architecture <RTL>).
Entity <OldOs> analyzed. Unit <OldOs> generated.

Analyzing Entity <PIA> in library <work> (Architecture <RTL>).
Entity <PIA> analyzed. Unit <PIA> generated.

Analyzing Entity <Ramdisk> in library <work> (Architecture <RTL>).
Entity <Ramdisk> analyzed. Unit <Ramdisk> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <FreezerLogic>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/FreezerLogic.vhd".
    Found finite state machine <FSM_0> for signal <next_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 16                                             |
    | Inputs             | 6                                              |
    | Outputs            | 6                                              |
    | Clock              | clk_register              (falling_edge)       |
    | Reset              | reset_n                   (negative)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | user                                           |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 5-bit register for signal <ram_bank>.
    Found 6-bit register for signal <rom_bank>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <use_status_as_ram_address<0>>.
    Found 1-bit register for signal <vector_a2>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 D-type flip-flop(s).
Unit <FreezerLogic> synthesized.


Synthesizing Unit <CartEmu>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/CartEmu.vhd".
    Found 7-bit register for signal <cfg_bank>.
    Found 1-bit register for signal <cfg_enable>.
    Found 1-bit register for signal <cfg_menu>.
    Found 3-bit register for signal <cfg_mode>.
    Found 1-bit register for signal <cfg_source_ram>.
    Found 6-bit register for signal <cfg_sram_bank>.
    Found 1-bit register for signal <cfg_sram_enable>.
    Found 2-bit register for signal <cfg_usdx>.
    Found 1-bit register for signal <cfg_write_enable>.
    Found 2-bit register for signal <oss_bank>.
    Found 6-bit register for signal <usdx_bank>.
    Found 2-bit register for signal <usdx_ctl>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <CartEmu> synthesized.


Synthesizing Unit <OldOs>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/OldOs.vhd".
Unit <OldOs> synthesized.


Synthesizing Unit <PIA>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/PIA.vhd".
    Found 1-bit register for signal <pia_crb2>.
    Found 8-bit register for signal <pia_ddrb>.
    Found 8-bit register for signal <pia_portb>.
Unit <PIA> synthesized.


Synthesizing Unit <Ramdisk>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/Ramdisk.vhd".
WARNING:Xst:647 - Input <portb<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Ramdisk> synthesized.


Synthesizing Unit <TurboFreezer>.
    Related source file is "/home/hias/private/xl/turbo-freezer/xilinx/svn/TurboFreezer.vhd".
WARNING:Xst:647 - Input <nc_adr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mpd_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <irq_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <extsel_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <merged_out.adr<11:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <merged_out.adr<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit tristate buffer for signal <d>.
    Found 1-bit tristate buffer for signal <refresh>.
    Found 2-bit register for signal <activate_n_sync>.
    Found 1-bit register for signal <powerup_n>.
    Found 4-bit register for signal <reset_n_sync>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   9 Tristate(s).
Unit <TurboFreezer> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 29
 1-bit register                                        : 16
 2-bit register                                        : 4
 3-bit register                                        : 2
 4-bit register                                        : 1
 5-bit register                                        : 1
 6-bit register                                        : 3
 8-bit register                                        : 2
# Tristates                                            : 2
 1-bit tristate buffer                                 : 1
 8-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Optimizing FSM <use_freezer/next_state/FSM> on signal <next_state[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 100   | 100
 101   | 101
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Registers                                            : 12
 Flip-Flops                                            : 12

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <TurboFreezer> ...
  implementation constraint: NOREDUCE	 : dout_enable
  implementation constraint: INIT=r	 : reset_n_sync_3
  implementation constraint: INIT=r	 : activate_n_sync_1
  implementation constraint: INIT=r	 : activate_n_sync_0
  implementation constraint: INIT=r	 : reset_n_sync_0
  implementation constraint: INIT=r	 : reset_n_sync_1
  implementation constraint: INIT=r	 : reset_n_sync_2
  implementation constraint: INIT=r	 : powerup_n
  implementation constraint: LOC=P46	 : activate_n_in
  implementation constraint: LOC=P24	 : ramdisk_enable_n
  implementation constraint: LOC=P19	 : flash_we_n
  implementation constraint: LOC=P43	 : oldos_n
  implementation constraint: LOC=P22	 : phi2
  implementation constraint: BUFG=clk	 : phi2
  implementation constraint: LOC=P99	 : reset_n_in
  implementation constraint: LOC=P33	 : rw
  implementation constraint: LOC=P34	 : dualpokey_n
  implementation constraint: LOC=P27	 : phi2short
  implementation constraint: BUFG=clk	 : phi2short
  implementation constraint: LOC=P7	 : cartemu_enable_n
  implementation constraint: LOC=P15	 : a<15>
  implementation constraint: LOC=P14	 : a<14>
  implementation constraint: LOC=P13	 : a<13>
  implementation constraint: LOC=P12	 : a<12>
  implementation constraint: LOC=P11	 : a<11>
  implementation constraint: LOC=P10	 : a<10>
  implementation constraint: LOC=P9	 : a<9>
  implementation constraint: LOC=P8	 : a<8>
  implementation constraint: LOC=P6	 : a<7>
  implementation constraint: LOC=P4	 : a<6>
  implementation constraint: LOC=P3	 : a<5>
  implementation constraint: LOC=P1	 : a<4>
  implementation constraint: LOC=P36	 : a<3>
  implementation constraint: LOC=P35	 : a<2>
  implementation constraint: LOC=P50	 : a<1>
  implementation constraint: LOC=P42	 : a<0>
  implementation constraint: LOC=P78	 : ram_rom_oe
  implementation constraint: LOC=P73	 : refresh
  implementation constraint: LOC=P77	 : ram_rom_we
  implementation constraint: LOC=P97	 : rom1_ce
  implementation constraint: LOC=P96	 : ram1_ce
  implementation constraint: LOC=P79	 : rom0_ce
  implementation constraint: LOC=P81	 : ram0_ce
  implementation constraint: LOC=P30	 : d<7>
  implementation constraint: LOC=P29	 : d<6>
  implementation constraint: LOC=P28	 : d<5>
  implementation constraint: LOC=P25	 : d<4>
  implementation constraint: LOC=P20	 : d<3>
  implementation constraint: LOC=P18	 : d<2>
  implementation constraint: LOC=P17	 : d<1>
  implementation constraint: LOC=P16	 : d<0>
  implementation constraint: LOC=P91	 : ram_rom_a<18>
  implementation constraint: LOC=P90	 : ram_rom_a<17>
  implementation constraint: LOC=P89	 : ram_rom_a<16>
  implementation constraint: LOC=P87	 : ram_rom_a<15>
  implementation constraint: LOC=P86	 : ram_rom_a<14>
  implementation constraint: LOC=P85	 : ram_rom_a<13>
  implementation constraint: LOC=P82	 : ram_rom_a<12>
  implementation constraint: LOC=P95	 : ram_a<7>
  implementation constraint: LOC=P94	 : ram_a<6>
  implementation constraint: LOC=P93	 : ram_a<5>
  implementation constraint: LOC=P92	 : ram_a<4>

Optimizing unit <OldOs> ...

Optimizing unit <Ramdisk> ...

Optimizing unit <FreezerLogic> ...
  implementation constraint: INIT=r	 : next_state_FSM_FFd3
  implementation constraint: INIT=r	 : use_status_as_ram_address_0
  implementation constraint: INIT=r	 : next_state_FSM_FFd2
  implementation constraint: INIT=r	 : next_state_FSM_FFd1
  implementation constraint: INIT=r	 : state_2
  implementation constraint: INIT=r	 : state_1
  implementation constraint: INIT=r	 : state_0

Optimizing unit <CartEmu> ...
  implementation constraint: KEEP	 : trig3_disable_atari
  implementation constraint: INIT=r	 : cfg_sram_bank_1
  implementation constraint: INIT=r	 : cfg_sram_bank_2
  implementation constraint: INIT=r	 : cfg_sram_bank_5
  implementation constraint: INIT=r	 : cfg_bank_0
  implementation constraint: INIT=r	 : usdx_bank_5
  implementation constraint: INIT=r	 : cfg_sram_bank_4
  implementation constraint: INIT=r	 : cfg_bank_6
  implementation constraint: INIT=r	 : cfg_sram_bank_0
  implementation constraint: INIT=r	 : usdx_ctl_0
  implementation constraint: INIT=r	 : usdx_bank_0
  implementation constraint: INIT=r	 : cfg_mode_0
  implementation constraint: INIT=r	 : usdx_bank_1
  implementation constraint: INIT=r	 : usdx_bank_2
  implementation constraint: INIT=r	 : usdx_bank_3
  implementation constraint: INIT=r	 : usdx_ctl_1
  implementation constraint: INIT=r	 : usdx_bank_4
  implementation constraint: INIT=r	 : cfg_bank_5
  implementation constraint: INIT=r	 : cfg_write_enable
  implementation constraint: INIT=r	 : cfg_sram_enable
  implementation constraint: INIT=r	 : cfg_bank_1
  implementation constraint: INIT=r	 : cfg_bank_2
  implementation constraint: INIT=r	 : cfg_menu
  implementation constraint: INIT=r	 : cfg_bank_3
  implementation constraint: INIT=r	 : cfg_bank_4
  implementation constraint: INIT=r	 : cfg_mode_1
  implementation constraint: INIT=r	 : cfg_mode_2
  implementation constraint: INIT=r	 : cfg_source_ram
  implementation constraint: INIT=r	 : cfg_sram_bank_3
  implementation constraint: INIT=r	 : cfg_enable
  implementation constraint: INIT=r	 : cfg_usdx_0
  implementation constraint: INIT=r	 : cfg_usdx_1
  implementation constraint: INIT=r	 : oss_bank_0
  implementation constraint: INIT=r	 : oss_bank_1

Optimizing unit <PIA> ...
WARNING:Xst:2677 - Node <pia_portb_0> of sequential type is unconnected in block <use_pia>.
WARNING:Xst:2677 - Node <pia_portb_1> of sequential type is unconnected in block <use_pia>.
WARNING:Xst:2677 - Node <pia_ddrb_0> of sequential type is unconnected in block <use_pia>.
WARNING:Xst:2677 - Node <pia_ddrb_1> of sequential type is unconnected in block <use_pia>.

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : TurboFreezer.ngr
Top Level Output File Name         : TurboFreezer
Output Format                      : NGC
Optimization Goal                  : Area
Keep Hierarchy                     : Yes
Target Technology                  : XC9500XL CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 59

Cell Usage :
# BELS                             : 1009
#      AND2                        : 391
#      AND3                        : 64
#      AND4                        : 6
#      GND                         : 4
#      INV                         : 316
#      OR2                         : 204
#      OR3                         : 22
#      XOR2                        : 2
# FlipFlops/Latches                : 72
#      FD                          : 12
#      FDCE                        : 60
# IO Buffers                       : 52
#      IBUF                        : 26
#      IOBUFE                      : 8
#      OBUF                        : 17
#      OBUFE                       : 1
=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 5.18 secs
 
--> 


Total memory usage is 352892 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   11 (   0 filtered)
Number of infos    :    0 (   0 filtered)

