MDF Database:  version 1.0
MDF_INFO | TurboFreezer | XC95144XL-10-TQ100
MACROCELL | 0 | 8 | merged_out_dout<0>
ATTRIBUTES | 265985 | 0
OUTPUTMC | 1 | 0 | 9
INPUTS | 20 | use_cartemu/trig3_disable_atari  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/state<1>  | freezer_mem_dout<5>/freezer_mem_dout<5>_D2  | a<6>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<2>  | dout_enable  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | rw  | a<1>  | d<2>.PIN  | a<3>  | a<0>  | $OpTx$FX_DC$499  | use_cartemu/cfg_bank<3>.EXP
INPUTMC | 12 | 7 | 14 | 3 | 17 | 6 | 1 | 3 | 12 | 7 | 6 | 0 | 3 | 7 | 7 | 0 | 15 | 6 | 5 | 5 | 15 | 3 | 6 | 0 | 7
INPUTP | 8 | 8 | 58 | 11 | 56 | 79 | 28 | 59 | 68
EXPORTS | 1 | 0 | 9
IMPORTS | 1 | 0 | 7
EQ | 16 | 
   d<0> = use_cartemu/trig3_disable_atari & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !use_freezer/state<1> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & freezer_mem_dout<5>/freezer_mem_dout<5>_D2
;Imported pterms FB1_8
	# rw & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/N50/use_cartemu/N50_D2;
   d<0>.OE = dout_enable;
    merged_out_dout<0>.EXP  =  a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & a<2> & !a<7> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<2>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499

MACROCELL | 2 | 8 | merged_out_dout<5>
ATTRIBUTES | 265985 | 0
INPUTS | 18 | merged_out_dout_or0000/merged_out_dout_or0000_D2  | freezer_mem_dout<5>/freezer_mem_dout<5>_D2  | rw  | a<6>  | a<5>  | a<1>  | a<2>  | use_cartemu/cfg_bank<5>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/cfg_sram_bank<5>  | use_cartemu/cfg_usdx<1>  | use_cartemu/usdx_bank<5>  | use_freezer/next_state_FSM_FFd1.EXP  | dout_enable
INPUTMC | 9 | 3 | 17 | 3 | 12 | 0 | 5 | 5 | 15 | 6 | 14 | 7 | 3 | 4 | 11 | 2 | 7 | 0 | 15
INPUTP | 9 | 56 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68
IMPORTS | 1 | 2 | 7
EQ | 18 | 
   d<5> = merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	freezer_mem_dout<5>/freezer_mem_dout<5>_D2
	# rw & !a<6> & !a<5> & a<1> & !a<2> & a<4> & a<7> & 
	use_cartemu/cfg_sram_bank<5> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & !a<6> & !a<5> & !a<1> & !a<2> & 
	use_cartemu/cfg_bank<5> & a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<5> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
;Imported pterms FB3_8
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<5> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2;
   d<5>.OE = dout_enable;

MACROCELL | 0 | 10 | merged_out_dout<1>
ATTRIBUTES | 265985 | 0
OUTPUTMC | 1 | 0 | 11
INPUTS | 16 | rw  | a<2>  | a<7>  | a<3>  | a<0>  | use_cartemu/usdx_bank<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/N97/use_cartemu/N97_D2  | a<1>  | use_cartemu/cfg_bank<1>  | $OpTx$FX_DC$499  | use_cartemu/cfg_sram_bank<1>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_bank<2>.EXP  | dout_enable
INPUTMC | 10 | 1 | 4 | 5 | 15 | 3 | 17 | 2 | 3 | 0 | 12 | 3 | 6 | 1 | 8 | 7 | 6 | 0 | 9 | 0 | 15
INPUTP | 6 | 56 | 58 | 11 | 59 | 68 | 79
EXPORTS | 1 | 0 | 11
IMPORTS | 1 | 0 | 9
EQ | 30 | 
   d<1> = rw & !a<2> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/N97/use_cartemu/N97_D2
	# rw & a<1> & !a<2> & a<7> & 
	use_cartemu/cfg_sram_bank<1> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & !a<1> & !a<2> & use_cartemu/cfg_bank<1> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
;Imported pterms FB1_10
	# rw & use_cartemu/cfg_mode<1> & !a<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & a<1> & use_cartemu/cfg_usdx<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & !a<1> & a<2> & a<7> & 
	use_cartemu/cfg_source_ram & !a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499;
   d<1>.OE = dout_enable;
    merged_out_dout<1>.EXP  =  rw & use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499

MACROCELL | 0 | 11 | merged_out_dout<2>
ATTRIBUTES | 265985 | 0
INPUTS | 16 | rw  | a<2>  | a<7>  | a<3>  | a<0>  | use_cartemu/usdx_bank<2>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/N97/use_cartemu/N97_D2  | a<1>  | use_cartemu/cfg_bank<2>  | $OpTx$FX_DC$499  | use_cartemu/cfg_sram_bank<2>  | use_cartemu/cfg_menu  | merged_out_dout<1>.EXP  | dout_enable
INPUTMC | 10 | 1 | 3 | 5 | 15 | 3 | 17 | 2 | 3 | 0 | 9 | 3 | 6 | 1 | 7 | 7 | 9 | 0 | 10 | 0 | 15
INPUTP | 6 | 56 | 58 | 11 | 59 | 68 | 79
IMPORTS | 1 | 0 | 10
EQ | 22 | 
   d<2> = rw & !a<2> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<2> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/N97/use_cartemu/N97_D2
	# rw & use_cartemu/cfg_menu & !a<1> & a<2> & a<7> & 
	!a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & a<1> & !a<2> & a<7> & 
	use_cartemu/cfg_sram_bank<2> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & !a<1> & !a<2> & use_cartemu/cfg_bank<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
;Imported pterms FB1_11
	# rw & use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499;
   d<2>.OE = dout_enable;

MACROCELL | 0 | 14 | merged_out_dout<3>
ATTRIBUTES | 265985 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 18 | rw  | a<6>  | a<5>  | a<1>  | a<2>  | use_cartemu/cfg_bank<3>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/cfg_sram_bank<3>  | phi2  | use_cartemu/cfg_usdx<0>  | use_cartemu/cfg_usdx<1>  | dout_enable  | use_cartemu/cfg_bank<0>.EXP
INPUTMC | 8 | 0 | 7 | 5 | 15 | 3 | 17 | 1 | 6 | 7 | 4 | 7 | 3 | 0 | 15 | 0 | 13
INPUTP | 10 | 56 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68 | 33
EXPORTS | 1 | 0 | 15
IMPORTS | 1 | 0 | 13
EQ | 22 | 
   d<3> = rw & !a<6> & !a<5> & a<1> & !a<2> & a<4> & a<7> & 
	use_cartemu/cfg_sram_bank<3> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & !a<6> & !a<5> & !a<1> & !a<2> & 
	use_cartemu/cfg_bank<3> & a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
;Imported pterms FB1_14
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2;
   d<3>.OE = dout_enable;
    merged_out_dout<3>.EXP  =  rw & a<6> & a<5> & phi2 & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & phi2 & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2

MACROCELL | 2 | 5 | merged_out_dout<4>
ATTRIBUTES | 265985 | 0
INPUTS | 17 | rw  | a<6>  | a<5>  | a<1>  | a<2>  | use_cartemu/cfg_bank<4>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/cfg_sram_bank<4>  | use_cartemu/cfg_usdx<1>  | use_cartemu/usdx_bank<4>  | use_cartemu/cfg_usdx<0>  | dout_enable
INPUTMC | 8 | 0 | 6 | 5 | 15 | 3 | 17 | 1 | 5 | 7 | 3 | 1 | 1 | 7 | 4 | 0 | 15
INPUTP | 9 | 56 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68
EQ | 15 | 
   d<4> = rw & !a<6> & !a<5> & a<1> & !a<2> & a<4> & a<7> & 
	use_cartemu/cfg_sram_bank<4> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & !a<6> & !a<5> & !a<1> & !a<2> & 
	use_cartemu/cfg_bank<4> & a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<4> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<4> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2;
   d<4>.OE = dout_enable;

MACROCELL | 2 | 10 | merged_out_dout<6>
ATTRIBUTES | 265985 | 0
INPUTS | 16 | rw  | a<6>  | a<5>  | a<1>  | a<2>  | a<4>  | a<7>  | use_cartemu/cfg_bank<6>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/cfg_usdx<1>  | use_cartemu/usdx_ctl<0>  | use_cartemu/cfg_usdx<0>  | dout_enable
INPUTMC | 7 | 2 | 9 | 5 | 15 | 3 | 17 | 7 | 3 | 1 | 11 | 7 | 4 | 0 | 15
INPUTP | 9 | 56 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68
EQ | 12 | 
   d<6> = rw & !a<6> & !a<5> & !a<1> & !a<2> & a<4> & a<7> & 
	use_cartemu/cfg_bank<6> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_ctl<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_ctl<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2;
   d<6>.OE = dout_enable;

MACROCELL | 2 | 11 | merged_out_dout<7>
ATTRIBUTES | 265985 | 0
INPUTS | 6 | rw  | use_cartemu/usdx_ctl<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/N97/use_cartemu/N97_D2  | dout_enable
INPUTMC | 5 | 1 | 10 | 5 | 15 | 3 | 17 | 2 | 3 | 0 | 15
INPUTP | 1 | 56
EQ | 4 | 
   d<7> = rw & use_cartemu/usdx_ctl<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/N97/use_cartemu/N97_D2;
   d<7>.OE = dout_enable;

MACROCELL | 7 | 6 | use_cartemu/cfg_mode<2>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 25 | 0 | 10 | 7 | 6 | 0 | 1 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 0 | 17 | 0 | 4 | 5 | 11 | 5 | 17 | 7 | 15 | 1 | 0 | 0 | 16 | 5 | 8 | 2 | 17 | 0 | 0 | 0 | 2 | 0 | 8 | 2 | 0 | 7 | 16
INPUTS | 12 | use_cartemu/cfg_mode<2>  | powerup_n  | reset_n_sync<1>  | rw  | a<1>  | a<2>  | a<7>  | d<2>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 5 | 7 | 6 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 56 | 79 | 58 | 11 | 28 | 59 | 68
EQ | 9 | 
   use_cartemu/cfg_mode<2>.T = use_cartemu/cfg_mode<2> & !powerup_n & 
	!reset_n_sync<1>
	# !rw & use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & !d<2>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & d<2>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_mode<2>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 3 | use_cartemu/cfg_mode<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 29 | 0 | 3 | 0 | 1 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 0 | 17 | 4 | 14 | 4 | 13 | 5 | 13 | 2 | 0 | 7 | 17 | 0 | 4 | 7 | 15 | 1 | 0 | 0 | 16 | 5 | 8 | 5 | 9 | 2 | 17 | 0 | 0 | 0 | 2 | 0 | 8 | 5 | 14 | 5 | 15 | 7 | 16
INPUTS | 12 | use_cartemu/cfg_mode<0>  | powerup_n  | reset_n_sync<1>  | rw  | a<1>  | a<2>  | a<7>  | d<0>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 5 | 0 | 3 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 56 | 79 | 58 | 11 | 24 | 59 | 68
EXPORTS | 1 | 0 | 2
EQ | 12 | 
   use_cartemu/cfg_mode<0>.T = use_cartemu/cfg_mode<0> & !powerup_n & 
	!reset_n_sync<1>
	# !rw & use_cartemu/cfg_mode<0> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<0> & !a<1> & a<2> & 
	a<7> & d<0>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_mode<0>.CLK = phi2short;	// GCK
    use_cartemu/cfg_mode<0>.EXP  =  !rw & a<1> & !a<2> & a<7> & !a<3> & !a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 7 | use_cartemu/cfg_mode<1>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 24 | 0 | 8 | 7 | 7 | 0 | 1 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 0 | 17 | 0 | 4 | 5 | 11 | 5 | 17 | 7 | 15 | 1 | 0 | 0 | 16 | 5 | 8 | 2 | 17 | 0 | 0 | 0 | 2 | 2 | 0 | 7 | 16
INPUTS | 12 | use_cartemu/cfg_mode<1>  | powerup_n  | reset_n_sync<1>  | rw  | a<1>  | a<2>  | a<7>  | d<1>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 5 | 7 | 7 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 56 | 79 | 58 | 11 | 26 | 59 | 68
EQ | 9 | 
   use_cartemu/cfg_mode<1>.T = use_cartemu/cfg_mode<1> & !powerup_n & 
	!reset_n_sync<1>
	# !rw & use_cartemu/cfg_mode<1> & !a<1> & a<2> & 
	a<7> & !d<1>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & a<2> & 
	a<7> & d<1>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_mode<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 9 | use_cartemu/cfg_menu
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 16 | 0 | 11 | 7 | 9 | 7 | 14 | 5 | 13 | 5 | 14 | 3 | 7 | 7 | 15 | 1 | 17 | 5 | 9 | 1 | 14 | 1 | 13 | 1 | 16 | 1 | 12 | 1 | 15 | 5 | 8 | 5 | 15
INPUTS | 13 | use_cartemu/cfg_menu  | powerup_n  | reset_n_sync<1>  | cartemu_enable_n  | rw  | a<1>  | a<2>  | a<7>  | d<2>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 5 | 7 | 9 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 8 | 12 | 56 | 79 | 58 | 11 | 28 | 59 | 68
EQ | 11 | 
   use_cartemu/cfg_menu.T = use_cartemu/cfg_menu & !powerup_n & 
	!reset_n_sync<1> & cartemu_enable_n
	# !use_cartemu/cfg_menu & !powerup_n & 
	!reset_n_sync<1> & !cartemu_enable_n
	# !rw & use_cartemu/cfg_menu & !a<1> & a<2> & a<7> & 
	!d<2>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_menu & !a<1> & a<2> & a<7> & 
	d<2>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_menu.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 15 | dout_enable
ATTRIBUTES | 133889 | 0
OUTPUTMC | 8 | 0 | 8 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 2 | 11
INPUTS | 15 | rw  | phi2  | use_cartemu/trig3_disable_atari  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | freezer_mem_dout<5>/freezer_mem_dout<5>_D2  | a<6>  | a<5>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<2>  | a<1>  | merged_out_dout<3>.EXP
INPUTMC | 5 | 7 | 14 | 3 | 17 | 3 | 12 | 5 | 15 | 0 | 14
INPUTP | 10 | 56 | 33 | 8 | 6 | 2 | 11 | 59 | 68 | 58 | 79
IMPORTS | 1 | 0 | 14
EQ | 20 | 
   dout_enable = rw & phi2 & use_cartemu/trig3_disable_atari & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & phi2 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & freezer_mem_dout<5>/freezer_mem_dout<5>_D2
	# rw & !a<6> & !a<5> & phi2 & !a<1> & a<4> & a<7> & 
	!a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & !a<6> & !a<5> & phi2 & !a<2> & a<4> & a<7> & 
	!a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & !a<6> & !a<5> & phi2 & a<4> & a<7> & !a<3> & 
	!a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
;Imported pterms FB1_15
	# rw & a<6> & a<5> & phi2 & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & phi2 & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2;

MACROCELL | 0 | 1 | use_cartemu/cfg_enable
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 7 | 0 | 1 | 7 | 14 | 7 | 17 | 5 | 8 | 0 | 0 | 0 | 2 | 0 | 17
INPUTS | 17 | use_cartemu/cfg_enable  | powerup_n  | reset_n_sync<1>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$508  | rw  | a<1>  | a<2>  | a<3>  | a<0>  | $OpTx$FX_DC$499  | EXP14_.EXP  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2.EXP
INPUTMC | 11 | 0 | 1 | 6 | 8 | 6 | 5 | 7 | 6 | 0 | 3 | 7 | 7 | 5 | 15 | 2 | 0 | 3 | 6 | 0 | 0 | 0 | 2
INPUTP | 6 | 11 | 56 | 79 | 58 | 59 | 68
IMPORTS | 2 | 0 | 0 | 0 | 2
EQ | 64 | 
   use_cartemu/cfg_enable.T = use_cartemu/cfg_enable & !powerup_n & 
	!reset_n_sync<1>
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !use_cartemu/cfg_enable & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & use_cartemu/cfg_enable & a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & 
	!use_cartemu/cfg_enable & !a<2> & a<7> & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & !use_cartemu/cfg_enable & !a<2> & 
	a<7> & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
;Imported pterms FB1_1
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & 
	!use_cartemu/cfg_enable & !a<2> & a<7> & d<0>.PIN & !a<3> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & !use_cartemu/cfg_enable & !a<2> & 
	a<7> & d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !rw & !use_cartemu/cfg_mode<0> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
;Imported pterms FB1_18
	# !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
;Imported pterms FB1_3
	# !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & use_cartemu/cfg_mode<2> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & use_cartemu/cfg_enable & !a<2> & 
	a<7> & !d<0>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508;
   !use_cartemu/cfg_enable.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 4 | use_cartemu/cfg_usdx<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 12 | 2 | 7 | 0 | 13 | 2 | 5 | 2 | 10 | 0 | 14 | 7 | 4 | 7 | 0 | 2 | 3 | 1 | 9 | 2 | 2 | 7 | 15 | 1 | 15
INPUTS | 12 | use_cartemu/cfg_usdx<0>  | powerup_n  | reset_n_sync<1>  | rw  | a<1>  | a<7>  | d<0>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
INPUTMC | 6 | 7 | 4 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6 | 0 | 2
INPUTP | 6 | 56 | 79 | 11 | 24 | 59 | 68
EQ | 11 | 
   use_cartemu/cfg_usdx<0>.T = use_cartemu/cfg_usdx<0> & !powerup_n & 
	!reset_n_sync<1>
	# !rw & a<1> & use_cartemu/cfg_usdx<0> & a<7> & 
	!d<0>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# !rw & a<1> & !use_cartemu/cfg_usdx<0> & a<7> & 
	d<0>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_usdx<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 3 | use_cartemu/cfg_usdx<1>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 13 | 2 | 8 | 0 | 9 | 0 | 13 | 2 | 5 | 2 | 10 | 0 | 14 | 7 | 3 | 7 | 0 | 2 | 3 | 1 | 9 | 2 | 2 | 7 | 15 | 1 | 15
INPUTS | 12 | use_cartemu/cfg_usdx<1>  | powerup_n  | reset_n_sync<1>  | rw  | a<1>  | a<7>  | d<1>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
INPUTMC | 6 | 7 | 3 | 6 | 8 | 6 | 5 | 5 | 15 | 3 | 6 | 0 | 2
INPUTP | 6 | 56 | 79 | 11 | 26 | 59 | 68
EQ | 11 | 
   use_cartemu/cfg_usdx<1>.T = use_cartemu/cfg_usdx<1> & !powerup_n & 
	!reset_n_sync<1>
	# !rw & a<1> & use_cartemu/cfg_usdx<1> & a<7> & 
	!d<1>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# !rw & a<1> & !use_cartemu/cfg_usdx<1> & a<7> & 
	d<1>.PIN & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_usdx<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 8 | powerup_n
ATTRIBUTES | 4358977 | 0
OUTPUTMC | 11 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 1 | 7 | 4 | 7 | 3 | 6 | 8 | 1 | 10 | 7 | 5 | 1 | 11
INPUTS | 3 | powerup_n  | reset_n_sync<2>  | reset_n_sync<3>
INPUTMC | 3 | 6 | 8 | 6 | 4 | 6 | 3
EQ | 3 | 
   powerup_n.T = Vcc;
   !powerup_n.CLK = phi2;	// GCK
   powerup_n.CE = !powerup_n & reset_n_sync<2> & !reset_n_sync<3>;
GLOBALS | 1 | 2 | phi2

MACROCELL | 7 | 8 | use_cartemu/cfg_sram_enable
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 7 | 8 | 7 | 17 | 1 | 0
INPUTS | 11 | use_cartemu/cfg_sram_enable  | reset_n_sync<1>  | rw  | a<1>  | a<2>  | a<7>  | d<0>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 4 | 7 | 8 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 56 | 79 | 58 | 11 | 24 | 59 | 68
EQ | 11 | 
   use_cartemu/cfg_sram_enable.T = use_cartemu/cfg_sram_enable & !reset_n_sync<1>
	# !rw & a<1> & use_cartemu/cfg_sram_enable & !a<2> & 
	a<7> & !d<0>.PIN & !a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & a<1> & !use_cartemu/cfg_sram_enable & !a<2> & 
	a<7> & d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & a<1> & !use_cartemu/cfg_sram_enable & !a<2> & 
	a<7> & !a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_sram_enable.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 10 | use_cartemu/usdx_ctl<1>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 2 | 11 | 1 | 10 | 2 | 2
INPUTS | 7 | powerup_n  | use_cartemu/usdx_ctl<1>  | reset_n_sync<1>  | rw  | d<7>.PIN  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 5 | 6 | 8 | 1 | 10 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 49
EQ | 9 | 
   use_cartemu/usdx_ctl<1>.T = !powerup_n & !use_cartemu/usdx_ctl<1> & 
	!reset_n_sync<1>
	# !rw & use_cartemu/usdx_ctl<1> & reset_n_sync<1> & 
	!d<7>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !use_cartemu/usdx_ctl<1> & reset_n_sync<1> & 
	d<7>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_ctl<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 13 | use_cartemu/cfg_bank<0>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 4 | 0 | 13 | 7 | 17 | 5 | 15 | 0 | 14
INPUTS | 21 | use_cartemu/cfg_bank<0>  | $OpTx$FX_DC$510  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | a<0>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<5>  | a<1>  | use_cartemu/cfg_usdx<0>  | a<2>  | a<4>  | a<3>  | use_cartemu/usdx_bank<3>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/cfg_usdx<1>  | use_cartemu/cfg_bank<1>.EXP
INPUTMC | 12 | 0 | 13 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 7 | 4 | 1 | 2 | 3 | 17 | 7 | 3 | 0 | 12
INPUTP | 9 | 11 | 68 | 8 | 56 | 6 | 79 | 58 | 2 | 59
EXPORTS | 1 | 0 | 14
IMPORTS | 1 | 0 | 12
EQ | 21 | 
   use_cartemu/cfg_bank<0>.D = use_cartemu/cfg_bank<0> & !$OpTx$FX_DC$510
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<7> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
;Imported pterms FB1_13
	# !rw & !a<1> & !a<2> & a<7> & d<0>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<0>.CLK = phi2short;	// GCK
    use_cartemu/cfg_bank<0>.EXP  =  rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
	# rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<1> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 12 | use_cartemu/cfg_bank<1>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 4 | 0 | 10 | 0 | 12 | 1 | 16 | 0 | 13
INPUTS | 17 | use_cartemu/cfg_bank<1>  | $OpTx$FX_DC$510  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<1>  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<2>  | d<1>.PIN  | a<3>  | a<0>  | $OpTx$FX_DC$499  | d<0>.PIN
INPUTMC | 8 | 0 | 12 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 9 | 79 | 11 | 8 | 56 | 58 | 26 | 59 | 68 | 24
EXPORTS | 1 | 0 | 13
EQ | 15 | 
   use_cartemu/cfg_bank<1>.D = use_cartemu/cfg_bank<1> & !$OpTx$FX_DC$510
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & a<1> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & a<1> & !a<7> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<1>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<1>.CLK = phi2short;	// GCK
    use_cartemu/cfg_bank<1>.EXP  =  !rw & !a<1> & !a<2> & a<7> & d<0>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 9 | use_cartemu/cfg_bank<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 4 | 0 | 11 | 0 | 9 | 1 | 14 | 0 | 10
INPUTS | 18 | use_cartemu/cfg_bank<2>  | $OpTx$FX_DC$510  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<2>  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | rw  | a<1>  | a<3>  | a<0>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$FX_DC$499  | use_cartemu/cfg_usdx<1>  | use_cartemu/cfg_source_ram  | merged_out_dout<0>.EXP
INPUTMC | 12 | 0 | 9 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 17 | 3 | 6 | 7 | 3 | 7 | 5 | 0 | 8
INPUTP | 6 | 58 | 11 | 56 | 79 | 59 | 68
EXPORTS | 1 | 0 | 10
IMPORTS | 1 | 0 | 8
EQ | 25 | 
   use_cartemu/cfg_bank<2>.D = use_cartemu/cfg_bank<2> & !$OpTx$FX_DC$510
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & a<2> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
;Imported pterms FB1_9
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & a<2> & !a<7> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<2>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<2>.CLK = phi2short;	// GCK
    use_cartemu/cfg_bank<2>.EXP  =  rw & use_cartemu/cfg_mode<1> & !a<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & a<1> & use_cartemu/cfg_usdx<1> & a<2> & 
	a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
	# rw & !a<1> & a<2> & a<7> & 
	use_cartemu/cfg_source_ram & !a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_DC$499
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 7 | use_cartemu/cfg_bank<3>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 4 | 0 | 14 | 0 | 7 | 1 | 13 | 0 | 8
INPUTS | 18 | use_cartemu/cfg_bank<3>  | $OpTx$FX_DC$510  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | a<3>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<1>  | a<2>  | d<3>.PIN  | a<0>  | $OpTx$FX_DC$499  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/N50/use_cartemu/N50_D2
INPUTMC | 10 | 0 | 7 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 6 | 3 | 17 | 7 | 17
INPUTP | 8 | 11 | 59 | 8 | 56 | 79 | 58 | 30 | 68
EXPORTS | 1 | 0 | 8
EQ | 15 | 
   use_cartemu/cfg_bank<3>.D = use_cartemu/cfg_bank<3> & !$OpTx$FX_DC$510
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<7> & a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & a<3> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<3>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<3>.CLK = phi2short;	// GCK
    use_cartemu/cfg_bank<3>.EXP  =  rw & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/N50/use_cartemu/N50_D2
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 6 | use_cartemu/cfg_bank<4>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 2 | 5 | 0 | 6 | 1 | 12
INPUTS | 17 | use_cartemu/cfg_bank<4>  | $OpTx$FX_DC$510  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<4>  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<1>  | a<2>  | d<4>.PIN  | a<3>  | a<0>  | $OpTx$FX_DC$499
INPUTMC | 8 | 0 | 6 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 9 | 2 | 11 | 8 | 56 | 79 | 58 | 37 | 59 | 68
EQ | 12 | 
   use_cartemu/cfg_bank<4>.D = use_cartemu/cfg_bank<4> & !$OpTx$FX_DC$510
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & a<4> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & a<4> & !a<7> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<4>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<4>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 5 | use_cartemu/cfg_bank<5>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 2 | 8 | 0 | 5 | 6 | 17
INPUTS | 17 | use_cartemu/cfg_bank<5>  | $OpTx$FX_DC$510  | a<5>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<1>  | a<2>  | d<5>.PIN  | a<3>  | a<0>  | $OpTx$FX_DC$499
INPUTMC | 8 | 0 | 5 | 0 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 9 | 6 | 11 | 8 | 56 | 79 | 58 | 44 | 59 | 68
EQ | 11 | 
   use_cartemu/cfg_bank<5>.D = use_cartemu/cfg_bank<5> & !$OpTx$FX_DC$510
	# a<5> & use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & a<5> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & d<5>.PIN & !a<3> & 
	!a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<5>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 14 | use_cartemu/trig3_disable_atari
ATTRIBUTES | 133889 | 0
OUTPUTMC | 3 | 0 | 8 | 0 | 15 | 5 | 6
INPUTS | 18 | rw  | a<9>  | a<8>  | a<10>  | use_cartemu/cfg_menu  | a<1>  | a<2>  | a<3>  | a<0>  | $OpTx$FX_DC$499  | $OpTx$FX_DC$521  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | use_cartemu/cfg_enable  | use_cartemu/cfg_mode<2>  | $OpTx$FX_DC$601
INPUTMC | 10 | 7 | 9 | 3 | 6 | 3 | 3 | 1 | 9 | 2 | 2 | 0 | 3 | 7 | 7 | 0 | 1 | 7 | 6 | 5 | 12
INPUTP | 8 | 56 | 15 | 13 | 17 | 79 | 58 | 59 | 68
EQ | 19 | 
   use_cartemu/trig3_disable_atari = rw & !a<9> & !a<8> & !a<10> & 
	use_cartemu/cfg_menu & a<1> & !a<2> & !a<3> & a<0> & $OpTx$FX_DC$499 & 
	$OpTx$FX_DC$521
	# rw & !a<9> & !a<8> & !a<10> & a<1> & !a<2> & 
	!a<3> & a<0> & $OpTx$FX_DC$499 & 
	!use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & $OpTx$FX_DC$521
	# rw & !a<9> & !a<8> & !a<10> & 
	use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & a<1> & 
	use_cartemu/cfg_enable & !a<2> & !a<3> & a<0> & $OpTx$FX_DC$499 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$521
	# rw & !a<9> & !a<8> & !a<10> & 
	use_cartemu/cfg_mode<0> & a<1> & use_cartemu/cfg_enable & !a<2> & !a<3> & 
	a<0> & $OpTx$FX_DC$499 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$521 & !$OpTx$FX_DC$601
	# rw & !a<9> & !a<8> & !a<10> & 
	!use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & a<1> & 
	use_cartemu/cfg_enable & !a<2> & !a<3> & a<0> & $OpTx$FX_DC$499 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$521;

MACROCELL | 2 | 9 | use_cartemu/cfg_bank<6>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 2 | 10 | 2 | 9 | 1 | 15
INPUTS | 15 | a<6>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | use_cartemu/cfg_bank<6>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | rw  | a<1>  | a<2>  | a<3>  | a<0>  | d<6>.PIN  | $OpTx$FX_DC$499
INPUTMC | 7 | 7 | 6 | 0 | 3 | 7 | 7 | 2 | 9 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 8 | 8 | 11 | 56 | 79 | 58 | 59 | 68 | 47
EQ | 15 | 
   use_cartemu/cfg_bank<6>.T = a<6> & use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & 
	!use_cartemu/cfg_bank<6> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !a<6> & use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cfg_bank<6> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & 
	use_cartemu/cfg_bank<6> & !a<3> & !a<0> & reset_n_sync<1> & !d<6>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & !a<2> & a<7> & 
	!use_cartemu/cfg_bank<6> & !a<3> & !a<0> & reset_n_sync<1> & d<6>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_bank<6>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 5 | use_cartemu/cfg_source_ram
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 0 | 9 | 7 | 5 | 7 | 15
INPUTS | 12 | powerup_n  | use_cartemu/cfg_source_ram  | reset_n_sync<1>  | rw  | a<1>  | a<2>  | a<7>  | d<1>.PIN  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499
INPUTMC | 5 | 6 | 8 | 7 | 5 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 56 | 79 | 58 | 11 | 26 | 59 | 68
EQ | 9 | 
   use_cartemu/cfg_source_ram.T = !powerup_n & use_cartemu/cfg_source_ram & 
	!reset_n_sync<1>
	# !rw & !a<1> & a<2> & a<7> & 
	use_cartemu/cfg_source_ram & !d<1>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & a<2> & a<7> & 
	!use_cartemu/cfg_source_ram & d<1>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
   !use_cartemu/cfg_source_ram.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 15 | use_cartemu/cfg_sram_bank<0>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 6 | 15 | 7 | 0 | 6 | 16
INPUTS | 3 | d<0>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<0>
INPUTMC | 2 | 0 | 2 | 6 | 15
INPUTP | 1 | 24
EQ | 5 | 
   use_cartemu/cfg_sram_bank<0>.D = d<0>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<0> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 8 | use_cartemu/cfg_sram_bank<1>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 0 | 10 | 1 | 8 | 1 | 16
INPUTS | 3 | d<1>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<1>
INPUTMC | 2 | 0 | 2 | 1 | 8
INPUTP | 1 | 26
EQ | 5 | 
   use_cartemu/cfg_sram_bank<1>.D = d<1>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<1> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 7 | use_cartemu/cfg_sram_bank<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 0 | 11 | 1 | 7 | 1 | 14
INPUTS | 3 | d<2>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<2>
INPUTMC | 2 | 0 | 2 | 1 | 7
INPUTP | 1 | 28
EQ | 5 | 
   use_cartemu/cfg_sram_bank<2>.D = d<2>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<2> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<2>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 6 | use_cartemu/cfg_sram_bank<3>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 0 | 14 | 1 | 6 | 1 | 13
INPUTS | 3 | d<3>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<3>
INPUTMC | 2 | 0 | 2 | 1 | 6
INPUTP | 1 | 30
EQ | 5 | 
   use_cartemu/cfg_sram_bank<3>.D = d<3>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<3> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<3>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 5 | use_cartemu/cfg_sram_bank<4>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 2 | 5 | 1 | 5 | 1 | 12
INPUTS | 3 | d<4>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<4>
INPUTMC | 2 | 0 | 2 | 1 | 5
INPUTP | 1 | 37
EQ | 5 | 
   use_cartemu/cfg_sram_bank<4>.D = d<4>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<4> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<4>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 14 | use_cartemu/cfg_sram_bank<5>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 2 | 8 | 6 | 14 | 6 | 17
INPUTS | 3 | d<5>.PIN  | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2  | use_cartemu/cfg_sram_bank<5>
INPUTMC | 2 | 0 | 2 | 6 | 14
INPUTP | 1 | 44
EQ | 5 | 
   use_cartemu/cfg_sram_bank<5>.D = d<5>.PIN & 
	use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
	# use_cartemu/cfg_sram_bank<5> & 
	!use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2;
   !use_cartemu/cfg_sram_bank<5>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 0 | 17 | use_cartemu/cfg_write_enable
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 5 | 0 | 17 | 7 | 17 | 1 | 17 | 0 | 16 | 0 | 0
INPUTS | 17 | use_cartemu/cfg_write_enable  | reset_n_sync<1>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<1>  | a<2>  | a<7>  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$508  | rw  | d<0>.PIN  | $OpTx$FX_DC$499  | use_cartemu/cfg_enable  | EXP15_.EXP
INPUTMC | 10 | 0 | 17 | 6 | 5 | 7 | 6 | 0 | 3 | 7 | 7 | 5 | 15 | 2 | 0 | 3 | 6 | 0 | 1 | 0 | 16
INPUTP | 7 | 79 | 58 | 11 | 59 | 68 | 56 | 24
EXPORTS | 1 | 0 | 0
IMPORTS | 1 | 0 | 16
EQ | 37 | 
   use_cartemu/cfg_write_enable.T = use_cartemu/cfg_write_enable & !reset_n_sync<1>
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & use_cartemu/cfg_write_enable & !a<3> & 
	a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & a<2> & a<7> & 
	use_cartemu/cfg_write_enable & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
;Imported pterms FB1_17
	# !rw & use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & use_cartemu/cfg_write_enable & !a<3> & 
	a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<0> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & use_cartemu/cfg_write_enable & !a<3> & 
	a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & a<2> & a<7> & d<0>.PIN & 
	!use_cartemu/cfg_write_enable & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & a<2> & a<7> & !d<0>.PIN & 
	use_cartemu/cfg_write_enable & !a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & a<2> & a<7> & 
	!use_cartemu/cfg_write_enable & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508;
   !use_cartemu/cfg_write_enable.CLK = phi2short;	// GCK
    use_cartemu/cfg_write_enable.EXP  =  !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 14 | use_cartemu/oss_bank<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 5 | 4 | 14 | 5 | 12 | 5 | 11 | 5 | 9 | 5 | 14
INPUTS | 8 | use_cartemu/cfg_mode<0>  | a<7>  | a<3>  | use_cartemu/oss_bank<0>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$508  | $OpTx$FX_DC$522
INPUTMC | 6 | 0 | 3 | 4 | 14 | 6 | 5 | 5 | 15 | 2 | 0 | 5 | 17
INPUTP | 2 | 11 | 59
EQ | 7 | 
   use_cartemu/oss_bank<0>.T = use_cartemu/cfg_mode<0> & !a<7> & a<3> & 
	use_cartemu/oss_bank<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$522
	# use_cartemu/cfg_mode<0> & !a<7> & !a<3> & 
	!use_cartemu/oss_bank<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$522;
   !use_cartemu/oss_bank<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 13 | use_cartemu/oss_bank<1>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 5 | 4 | 13 | 5 | 12 | 5 | 9 | 5 | 11 | 5 | 15
INPUTS | 8 | use_cartemu/cfg_mode<0>  | a<7>  | a<0>  | use_cartemu/oss_bank<1>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$508  | $OpTx$FX_DC$522
INPUTMC | 6 | 0 | 3 | 4 | 13 | 6 | 5 | 5 | 15 | 2 | 0 | 5 | 17
INPUTP | 2 | 11 | 68
EQ | 7 | 
   use_cartemu/oss_bank<1>.T = use_cartemu/cfg_mode<0> & !a<7> & a<0> & 
	!use_cartemu/oss_bank<1> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$522
	# use_cartemu/cfg_mode<0> & !a<7> & !a<0> & 
	use_cartemu/oss_bank<1> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$522;
   !use_cartemu/oss_bank<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 12 | use_cartemu/usdx_bank<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 4 | 12 | 7 | 0 | 6 | 16
INPUTS | 6 | rw  | d<0>.PIN  | use_cartemu/usdx_bank<0>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 4 | 12 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 24
EQ | 7 | 
   use_cartemu/usdx_bank<0>.T = !rw & d<0>.PIN & !use_cartemu/usdx_bank<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<0>.PIN & use_cartemu/usdx_bank<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 4 | use_cartemu/usdx_bank<1>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 0 | 10 | 1 | 4 | 1 | 16
INPUTS | 6 | rw  | d<1>.PIN  | use_cartemu/usdx_bank<1>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 1 | 4 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 26
EQ | 7 | 
   use_cartemu/usdx_bank<1>.T = !rw & d<1>.PIN & !use_cartemu/usdx_bank<1> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<1>.PIN & use_cartemu/usdx_bank<1> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<1>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 3 | use_cartemu/usdx_bank<2>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 0 | 11 | 1 | 3 | 1 | 14
INPUTS | 6 | rw  | d<2>.PIN  | use_cartemu/usdx_bank<2>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 1 | 3 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 28
EQ | 7 | 
   use_cartemu/usdx_bank<2>.T = !rw & d<2>.PIN & !use_cartemu/usdx_bank<2> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<2>.PIN & use_cartemu/usdx_bank<2> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<2>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 2 | use_cartemu/usdx_bank<3>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 0 | 13 | 1 | 2 | 1 | 13
INPUTS | 6 | rw  | d<3>.PIN  | use_cartemu/usdx_bank<3>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 1 | 2 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 30
EQ | 7 | 
   use_cartemu/usdx_bank<3>.T = !rw & d<3>.PIN & !use_cartemu/usdx_bank<3> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<3>.PIN & use_cartemu/usdx_bank<3> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<3>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 1 | use_cartemu/usdx_bank<4>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 2 | 5 | 1 | 1 | 1 | 12
INPUTS | 6 | rw  | d<4>.PIN  | use_cartemu/usdx_bank<4>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 1 | 1 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 37
EQ | 7 | 
   use_cartemu/usdx_bank<4>.T = !rw & d<4>.PIN & !use_cartemu/usdx_bank<4> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<4>.PIN & use_cartemu/usdx_bank<4> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<4>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 11 | use_cartemu/usdx_bank<5>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 4 | 2 | 8 | 4 | 11 | 6 | 17 | 2 | 7
INPUTS | 6 | rw  | d<5>.PIN  | use_cartemu/usdx_bank<5>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 4 | 4 | 11 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 44
EQ | 7 | 
   use_cartemu/usdx_bank<5>.T = !rw & d<5>.PIN & !use_cartemu/usdx_bank<5> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !d<5>.PIN & use_cartemu/usdx_bank<5> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_bank<5>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 1 | 11 | use_cartemu/usdx_ctl<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 2 | 10 | 1 | 11 | 1 | 9
INPUTS | 7 | powerup_n  | use_cartemu/usdx_ctl<0>  | reset_n_sync<1>  | rw  | d<6>.PIN  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2
INPUTMC | 5 | 6 | 8 | 1 | 11 | 6 | 5 | 5 | 15 | 2 | 3
INPUTP | 2 | 56 | 47
EQ | 9 | 
   use_cartemu/usdx_ctl<0>.T = !powerup_n & use_cartemu/usdx_ctl<0> & 
	!reset_n_sync<1>
	# !rw & use_cartemu/usdx_ctl<0> & reset_n_sync<1> & 
	!d<6>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# !rw & !use_cartemu/usdx_ctl<0> & reset_n_sync<1> & 
	d<6>.PIN & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2;
   !use_cartemu/usdx_ctl<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 2 | use_pia/pia_crb2
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 7 | 2 | 7 | 1
INPUTS | 13 | use_pia/pia_crb2  | reset_n_sync<1>  | rw  | a<9>  | a<8>  | a<1>  | a<2>  | d<2>.PIN  | a<3>  | a<0>  | $OpTx$FX_DC$508  | $OpTx$FX_DC$521  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
INPUTMC | 5 | 7 | 2 | 6 | 5 | 2 | 0 | 3 | 3 | 4 | 0
INPUTP | 8 | 56 | 15 | 13 | 79 | 58 | 28 | 59 | 68
EQ | 10 | 
   use_pia/pia_crb2.T = use_pia/pia_crb2 & !reset_n_sync<1>
	# !rw & a<9> & a<8> & a<1> & !a<2> & !d<2>.PIN & 
	!a<3> & a<0> & use_pia/pia_crb2 & $OpTx$FX_DC$508 & 
	$OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# !rw & a<9> & a<8> & a<1> & !a<2> & d<2>.PIN & 
	!a<3> & a<0> & !use_pia/pia_crb2 & reset_n_sync<1> & 
	$OpTx$FX_DC$508 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2;
   !use_pia/pia_crb2.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 16 | use_freezer/ram_bank_0
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 2 | 16 | 5 | 12
INPUTS | 13 | use_freezer/ram_bank_0  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<13>  | a<0>  | a<12>  | $OpTx$FX_SC$586
INPUTMC | 5 | 2 | 16 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 2
INPUTP | 8 | 22 | 23 | 18 | 8 | 6 | 21 | 68 | 19
EQ | 15 | 
   use_freezer/ram_bank_0.T = use_freezer/ram_bank_0 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	!a<0> & a<12> & use_freezer/ram_bank_0 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<0> & a<12> & !use_freezer/ram_bank_0 & 
	use_freezer/next_state_FSM_FFd1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<0> & a<12> & !use_freezer/ram_bank_0 & 
	use_freezer/next_state_FSM_FFd3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<0> & a<12> & !use_freezer/ram_bank_0 & 
	use_freezer/next_state_FSM_FFd2 & $OpTx$FX_SC$586;
   !use_freezer/ram_bank_0.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 15 | use_freezer/ram_bank_1
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 2 | 15 | 5 | 15
INPUTS | 13 | use_freezer/ram_bank_1  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<1>  | a<13>  | a<12>  | $OpTx$FX_SC$586
INPUTMC | 5 | 2 | 15 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 2
INPUTP | 8 | 22 | 23 | 18 | 8 | 6 | 79 | 21 | 19
EQ | 15 | 
   use_freezer/ram_bank_1.T = use_freezer/ram_bank_1 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<1> & 
	!a<13> & a<12> & use_freezer/ram_bank_1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & a<1> & 
	!a<13> & a<12> & !use_freezer/ram_bank_1 & 
	use_freezer/next_state_FSM_FFd1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & a<1> & 
	!a<13> & a<12> & !use_freezer/ram_bank_1 & 
	use_freezer/next_state_FSM_FFd3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & a<1> & 
	!a<13> & a<12> & !use_freezer/ram_bank_1 & 
	use_freezer/next_state_FSM_FFd2 & $OpTx$FX_SC$586;
   !use_freezer/ram_bank_1.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 14 | use_freezer/ram_bank_2
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 2 | 14 | 5 | 17
INPUTS | 13 | use_freezer/ram_bank_2  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<13>  | a<2>  | a<12>  | $OpTx$FX_SC$586
INPUTMC | 5 | 2 | 14 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 2
INPUTP | 8 | 22 | 23 | 18 | 8 | 6 | 21 | 58 | 19
EQ | 15 | 
   use_freezer/ram_bank_2.T = use_freezer/ram_bank_2 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	!a<2> & a<12> & use_freezer/ram_bank_2 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<2> & a<12> & !use_freezer/ram_bank_2 & 
	use_freezer/next_state_FSM_FFd1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<2> & a<12> & !use_freezer/ram_bank_2 & 
	use_freezer/next_state_FSM_FFd3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<2> & a<12> & !use_freezer/ram_bank_2 & 
	use_freezer/next_state_FSM_FFd2 & $OpTx$FX_SC$586;
   !use_freezer/ram_bank_2.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 13 | use_freezer/ram_bank_3
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 2 | 13 | 3 | 1
INPUTS | 13 | use_freezer/ram_bank_3  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<13>  | a<3>  | a<12>  | $OpTx$FX_SC$586
INPUTMC | 5 | 2 | 13 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 2
INPUTP | 8 | 22 | 23 | 18 | 8 | 6 | 21 | 59 | 19
EQ | 15 | 
   use_freezer/ram_bank_3.T = use_freezer/ram_bank_3 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	!a<3> & a<12> & use_freezer/ram_bank_3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<3> & a<12> & !use_freezer/ram_bank_3 & 
	use_freezer/next_state_FSM_FFd1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<3> & a<12> & !use_freezer/ram_bank_3 & 
	use_freezer/next_state_FSM_FFd3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<3> & a<12> & !use_freezer/ram_bank_3 & 
	use_freezer/next_state_FSM_FFd2 & $OpTx$FX_SC$586;
   !use_freezer/ram_bank_3.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 12 | use_freezer/ram_bank_4
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 2 | 12 | 3 | 3
INPUTS | 13 | use_freezer/ram_bank_4  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<13>  | a<4>  | a<12>  | $OpTx$FX_SC$586
INPUTMC | 5 | 2 | 12 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 2
INPUTP | 8 | 22 | 23 | 18 | 8 | 6 | 21 | 2 | 19
EQ | 15 | 
   use_freezer/ram_bank_4.T = use_freezer/ram_bank_4 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	!a<4> & a<12> & use_freezer/ram_bank_4 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<4> & a<12> & !use_freezer/ram_bank_4 & 
	use_freezer/next_state_FSM_FFd1 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<4> & a<12> & !use_freezer/ram_bank_4 & 
	use_freezer/next_state_FSM_FFd3 & $OpTx$FX_SC$586
	# a<14> & a<15> & !a<11> & !a<6> & !a<5> & !a<13> & 
	a<4> & a<12> & !use_freezer/ram_bank_4 & 
	use_freezer/next_state_FSM_FFd2 & $OpTx$FX_SC$586;
   !use_freezer/ram_bank_4.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 13 | use_freezer/rom_bank_0
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 7 | 13 | 5 | 15
INPUTS | 10 | use_freezer/rom_bank_0  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<0>  | $OpTx$FX_DC$521
INPUTMC | 5 | 7 | 13 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 68
EQ | 12 | 
   use_freezer/rom_bank_0.T = use_freezer/rom_bank_0 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & !a<0> & 
	use_freezer/rom_bank_0 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<0> & 
	!use_freezer/rom_bank_0 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<0> & 
	!use_freezer/rom_bank_0 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<0> & 
	!use_freezer/rom_bank_0 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_0.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 12 | use_freezer/rom_bank_1
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 7 | 12 | 5 | 17
INPUTS | 10 | use_freezer/rom_bank_1  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<1>  | $OpTx$FX_DC$521
INPUTMC | 5 | 7 | 12 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 79
EQ | 12 | 
   use_freezer/rom_bank_1.T = use_freezer/rom_bank_1 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & !a<1> & 
	use_freezer/rom_bank_1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<1> & 
	!use_freezer/rom_bank_1 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<1> & 
	!use_freezer/rom_bank_1 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & a<1> & 
	!use_freezer/rom_bank_1 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_1.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 11 | use_freezer/rom_bank_2
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 7 | 11 | 3 | 0
INPUTS | 10 | use_freezer/rom_bank_2  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<2>  | $OpTx$FX_DC$521
INPUTMC | 5 | 7 | 11 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 58
EQ | 12 | 
   use_freezer/rom_bank_2.T = !use_freezer/rom_bank_2 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & a<2> & 
	!use_freezer/rom_bank_2 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<2> & 
	use_freezer/rom_bank_2 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<2> & 
	use_freezer/rom_bank_2 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<2> & 
	use_freezer/rom_bank_2 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_2.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 17 | use_freezer/rom_bank_3
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 4 | 17 | 3 | 3
INPUTS | 10 | use_freezer/rom_bank_3  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<3>  | $OpTx$FX_DC$521
INPUTMC | 5 | 4 | 17 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 59
EQ | 12 | 
   use_freezer/rom_bank_3.T = !use_freezer/rom_bank_3 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & a<3> & 
	!use_freezer/rom_bank_3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<3> & 
	use_freezer/rom_bank_3 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<3> & 
	use_freezer/rom_bank_3 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<3> & 
	use_freezer/rom_bank_3 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_3.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 16 | use_freezer/rom_bank_4
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 4 | 16 | 3 | 4
INPUTS | 10 | use_freezer/rom_bank_4  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<4>  | $OpTx$FX_DC$521
INPUTMC | 5 | 4 | 16 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 2
EQ | 12 | 
   use_freezer/rom_bank_4.T = !use_freezer/rom_bank_4 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & a<4> & 
	!use_freezer/rom_bank_4 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<4> & 
	use_freezer/rom_bank_4 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<4> & 
	use_freezer/rom_bank_4 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<4> & 
	use_freezer/rom_bank_4 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_4.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 15 | use_freezer/rom_bank_5
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 2 | 4 | 15 | 3 | 6
INPUTS | 10 | use_freezer/rom_bank_5  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | a<9>  | a<8>  | a<10>  | a<6>  | a<5>  | $OpTx$FX_DC$521
INPUTMC | 5 | 4 | 15 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3
INPUTP | 5 | 15 | 13 | 17 | 8 | 6
EQ | 12 | 
   use_freezer/rom_bank_5.T = !use_freezer/rom_bank_5 & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# a<9> & a<8> & a<10> & a<6> & a<5> & 
	!use_freezer/rom_bank_5 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<5> & 
	use_freezer/rom_bank_5 & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<5> & 
	use_freezer/rom_bank_5 & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521
	# a<9> & a<8> & a<10> & a<6> & !a<5> & 
	use_freezer/rom_bank_5 & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521;
   !use_freezer/rom_bank_5.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 7 | 10 | use_freezer/use_status_as_ram_address<0>
ATTRIBUTES | 4358913 | 0
OUTPUTMC | 3 | 7 | 10 | 3 | 8 | 3 | 10
INPUTS | 12 | use_freezer/use_status_as_ram_address<0>  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | rw  | a<9>  | a<8>  | a<10>  | a<6>  | a<5>  | $OpTx$FX_DC$521  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
INPUTMC | 6 | 7 | 10 | 2 | 7 | 2 | 4 | 2 | 6 | 3 | 3 | 4 | 0
INPUTP | 6 | 56 | 15 | 13 | 17 | 8 | 6
EQ | 16 | 
   use_freezer/use_status_as_ram_address<0>.T = use_freezer/use_status_as_ram_address<0> & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2
	# !rw & a<9> & a<8> & a<10> & !a<6> & !a<5> & 
	use_freezer/use_status_as_ram_address<0> & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# rw & a<9> & a<8> & a<10> & !a<6> & !a<5> & 
	!use_freezer/use_status_as_ram_address<0> & use_freezer/next_state_FSM_FFd1 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# rw & a<9> & a<8> & a<10> & !a<6> & !a<5> & 
	!use_freezer/use_status_as_ram_address<0> & use_freezer/next_state_FSM_FFd3 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# rw & a<9> & a<8> & a<10> & !a<6> & !a<5> & 
	!use_freezer/use_status_as_ram_address<0> & use_freezer/next_state_FSM_FFd2 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2;
   !use_freezer/use_status_as_ram_address<0>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 1 | use_freezer/vector_a2
ATTRIBUTES | 8553281 | 0
OUTPUTMC | 2 | 3 | 8 | 2 | 0
INPUTS | 18 | a<2>  | a<14>  | a<15>  | rw  | a<11>  | a<6>  | a<5>  | a<13>  | a<4>  | a<3>  | a<0>  | a<12>  | reset_n_sync<1>  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_FSM_FFd2  | activate_n_sync<1>  | $OpTx$FX_SC$586
INPUTMC | 6 | 6 | 5 | 2 | 7 | 2 | 4 | 2 | 6 | 6 | 9 | 3 | 2
INPUTP | 12 | 58 | 22 | 23 | 56 | 18 | 8 | 6 | 21 | 2 | 59 | 68 | 19
EXPORTS | 1 | 2 | 0
EQ | 7 | 
   use_freezer/vector_a2.D = a<2>;
   !use_freezer/vector_a2.CLK = phi2short;	// GCK
   use_freezer/vector_a2.CE = a<14> & a<15> & rw & a<11> & a<6> & a<5> & 
	a<13> & a<4> & a<3> & !a<0> & a<12> & reset_n_sync<1> & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2 & !activate_n_sync<1> & $OpTx$FX_SC$586;
    use_freezer/vector_a2.EXP  =  !a<6> & !a<5> & !a<4>
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 10 | use_pia/pia_ddrb<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 10 | 5 | 16
INPUTS | 4 | use_pia/pia_ddrb<2>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | d<2>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 10 | 7 | 1 | 6 | 5
INPUTP | 1 | 28
EQ | 5 | 
   use_pia/pia_ddrb<2>.D = use_pia/pia_ddrb<2> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# d<2>.PIN & reset_n_sync<1> & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<2>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 9 | use_pia/pia_ddrb<3>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 9 | 3 | 1
INPUTS | 4 | use_pia/pia_ddrb<3>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | d<3>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 9 | 7 | 1 | 6 | 5
INPUTP | 1 | 30
EQ | 5 | 
   use_pia/pia_ddrb<3>.D = use_pia/pia_ddrb<3> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# d<3>.PIN & reset_n_sync<1> & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<3>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 8 | use_pia/pia_ddrb<4>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 8 | 6 | 7
INPUTS | 4 | use_pia/pia_ddrb<4>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | d<4>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 8 | 7 | 1 | 6 | 5
INPUTP | 1 | 37
EQ | 5 | 
   use_pia/pia_ddrb<4>.D = use_pia/pia_ddrb<4> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# d<4>.PIN & reset_n_sync<1> & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<4>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 7 | use_pia/pia_ddrb<5>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 7 | 3 | 4
INPUTS | 4 | use_pia/pia_ddrb<5>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | d<5>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 7 | 7 | 1 | 6 | 5
INPUTP | 1 | 44
EQ | 5 | 
   use_pia/pia_ddrb<5>.D = use_pia/pia_ddrb<5> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# d<5>.PIN & reset_n_sync<1> & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<5>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 6 | use_pia/pia_ddrb<6>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 6 | 3 | 5
INPUTS | 4 | use_pia/pia_ddrb<6>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | reset_n_sync<1>  | d<6>.PIN
INPUTMC | 3 | 4 | 6 | 7 | 1 | 6 | 5
INPUTP | 1 | 47
EQ | 5 | 
   use_pia/pia_ddrb<6>.D = use_pia/pia_ddrb<6> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# reset_n_sync<1> & d<6>.PIN & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<6>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 5 | use_pia/pia_ddrb<7>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 5 | 3 | 7
INPUTS | 4 | use_pia/pia_ddrb<7>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2  | reset_n_sync<1>  | d<7>.PIN
INPUTMC | 3 | 4 | 5 | 7 | 1 | 6 | 5
INPUTP | 1 | 49
EQ | 5 | 
   use_pia/pia_ddrb<7>.D = use_pia/pia_ddrb<7> & 
	!use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
	# reset_n_sync<1> & d<7>.PIN & 
	use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2;
   !use_pia/pia_ddrb<7>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 4 | use_pia/pia_portb<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 4 | 5 | 17
INPUTS | 4 | use_pia/pia_portb<2>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | d<2>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 4 | 7 | 0 | 6 | 5
INPUTP | 1 | 28
EQ | 5 | 
   use_pia/pia_portb<2>.D = use_pia/pia_portb<2> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# d<2>.PIN & reset_n_sync<1> & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<2>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 3 | use_pia/pia_portb<3>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 3 | 3 | 1
INPUTS | 4 | use_pia/pia_portb<3>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | d<3>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 3 | 7 | 0 | 6 | 5
INPUTP | 1 | 30
EQ | 5 | 
   use_pia/pia_portb<3>.D = use_pia/pia_portb<3> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# d<3>.PIN & reset_n_sync<1> & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<3>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 4 | 2 | use_pia/pia_portb<4>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 4 | 2 | 6 | 7
INPUTS | 4 | use_pia/pia_portb<4>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | d<4>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 4 | 2 | 7 | 0 | 6 | 5
INPUTP | 1 | 37
EQ | 5 | 
   use_pia/pia_portb<4>.D = use_pia/pia_portb<4> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# d<4>.PIN & reset_n_sync<1> & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<4>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 13 | use_pia/pia_portb<5>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 6 | 13 | 3 | 3
INPUTS | 4 | use_pia/pia_portb<5>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | d<5>.PIN  | reset_n_sync<1>
INPUTMC | 3 | 6 | 13 | 7 | 0 | 6 | 5
INPUTP | 1 | 44
EQ | 5 | 
   use_pia/pia_portb<5>.D = use_pia/pia_portb<5> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# d<5>.PIN & reset_n_sync<1> & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<5>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 12 | use_pia/pia_portb<6>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 6 | 12 | 3 | 5
INPUTS | 4 | use_pia/pia_portb<6>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | reset_n_sync<1>  | d<6>.PIN
INPUTMC | 3 | 6 | 12 | 7 | 0 | 6 | 5
INPUTP | 1 | 47
EQ | 5 | 
   use_pia/pia_portb<6>.D = use_pia/pia_portb<6> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# reset_n_sync<1> & d<6>.PIN & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<6>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 11 | use_pia/pia_portb<7>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 6 | 11 | 3 | 7
INPUTS | 4 | use_pia/pia_portb<7>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2  | reset_n_sync<1>  | d<7>.PIN
INPUTMC | 3 | 6 | 11 | 7 | 0 | 6 | 5
INPUTP | 1 | 49
EQ | 5 | 
   use_pia/pia_portb<7>.D = use_pia/pia_portb<7> & 
	!use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
	# reset_n_sync<1> & d<7>.PIN & 
	use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2;
   !use_pia/pia_portb<7>.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 5 | reset_n_sync<1>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 52 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 1 | 10 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 14 | 4 | 13 | 4 | 12 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 1 | 4 | 11 | 1 | 11 | 7 | 2 | 2 | 1 | 4 | 10 | 4 | 9 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 4 | 4 | 3 | 4 | 2 | 6 | 13 | 6 | 12 | 6 | 11 | 2 | 7 | 2 | 4 | 2 | 6 | 6 | 4 | 0 | 0 | 0 | 4 | 7 | 1 | 7 | 0 | 0 | 2 | 0 | 8 | 0 | 16
INPUTS | 1 | reset_n_sync<0>
INPUTMC | 1 | 6 | 6
EQ | 2 | 
   reset_n_sync<1>.D = reset_n_sync<0>;
   !reset_n_sync<1>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 1 | use_freezer/state<1>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 8 | 0 | 8 | 5 | 10 | 3 | 17 | 3 | 12 | 3 | 9 | 3 | 0 | 5 | 5 | 3 | 16
INPUTS | 1 | use_freezer/next_state_FSM_FFd2
INPUTMC | 1 | 2 | 6
EQ | 2 | 
   use_freezer/state<1>.D = use_freezer/next_state_FSM_FFd2;
   !use_freezer/state<1>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 0 | use_freezer/state<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 7 | 5 | 10 | 3 | 17 | 3 | 12 | 3 | 9 | 3 | 0 | 5 | 5 | 3 | 16
INPUTS | 1 | use_freezer/next_state_FSM_FFd1
INPUTMC | 1 | 2 | 7
EQ | 2 | 
   use_freezer/state<2>.D = use_freezer/next_state_FSM_FFd1;
   !use_freezer/state<2>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 2 | 7 | use_freezer/next_state_FSM_FFd1
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 18 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 2 | 1 | 6 | 0 | 2 | 7 | 2 | 4 | 2 | 6 | 2 | 8
INPUTS | 18 | reset_n_sync<1>  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2  | rw  | use_freezer/next_state_FSM_FFd2  | $OpTx$FX_DC$580  | a<6>  | a<5>  | a<1>  | use_cartemu/cfg_usdx<0>  | a<2>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/usdx_bank<5>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2
INPUTMC | 9 | 6 | 5 | 2 | 7 | 4 | 0 | 2 | 6 | 4 | 1 | 7 | 4 | 4 | 11 | 5 | 15 | 3 | 17
INPUTP | 9 | 56 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68
EXPORTS | 1 | 2 | 8
EQ | 11 | 
   use_freezer/next_state_FSM_FFd1.D = !rw & reset_n_sync<1> & 
	use_freezer/next_state_FSM_FFd1
	# reset_n_sync<1> & use_freezer/next_state_FSM_FFd1 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# reset_n_sync<1> & use_freezer/next_state_FSM_FFd2 & 
	$OpTx$FX_DC$580;
   !use_freezer/next_state_FSM_FFd1.CLK = phi2short;	// GCK
    use_freezer/next_state_FSM_FFd1.EXP  =  rw & a<6> & a<5> & !a<1> & 
	use_cartemu/cfg_usdx<0> & !a<2> & !a<4> & a<7> & !a<3> & !a<0> & 
	use_cartemu/usdx_bank<5> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & !merged_out_dout_or0000/merged_out_dout_or0000_D2
GLOBALS | 1 | 2 | phi2short

MACROCELL | 2 | 4 | use_freezer/next_state_FSM_FFd3
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 16 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 2 | 1 | 2 | 4 | 6 | 2 | 2 | 6
INPUTS | 18 | reset_n_sync<1>  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2  | rw  | a<14>  | a<15>  | a<11>  | a<6>  | a<5>  | a<13>  | a<4>  | a<3>  | a<0>  | a<12>  | use_freezer/next_state_FSM_FFd2  | activate_n_sync<1>  | $OpTx$FX_SC$586
INPUTMC | 7 | 6 | 5 | 2 | 7 | 2 | 4 | 4 | 0 | 2 | 6 | 6 | 9 | 3 | 2
INPUTP | 11 | 56 | 22 | 23 | 18 | 8 | 6 | 21 | 2 | 59 | 68 | 19
EQ | 11 | 
   use_freezer/next_state_FSM_FFd3.D = reset_n_sync<1> & use_freezer/next_state_FSM_FFd1 & 
	use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# !rw & reset_n_sync<1> & 
	use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
	# a<14> & a<15> & rw & a<11> & a<6> & a<5> & 
	a<13> & a<4> & a<3> & !a<0> & a<12> & reset_n_sync<1> & 
	!use_freezer/next_state_FSM_FFd1 & !use_freezer/next_state_FSM_FFd3 & 
	!use_freezer/next_state_FSM_FFd2 & !activate_n_sync<1> & $OpTx$FX_SC$586;
   !use_freezer/next_state_FSM_FFd3.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 2 | use_freezer/state<0>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 6 | 5 | 10 | 3 | 17 | 3 | 12 | 3 | 9 | 5 | 5 | 3 | 16
INPUTS | 1 | use_freezer/next_state_FSM_FFd3
INPUTMC | 1 | 2 | 4
EQ | 2 | 
   use_freezer/state<0>.D = use_freezer/next_state_FSM_FFd3;
   !use_freezer/state<0>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 2 | 6 | use_freezer/next_state_FSM_FFd2
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 2 | 1 | 6 | 1 | 2 | 7 | 2 | 4 | 2 | 6
INPUTS | 18 | reset_n_sync<1>  | use_freezer/next_state_FSM_FFd2  | $OpTx$FX_DC$580  | a<14>  | a<15>  | rw  | a<11>  | a<6>  | a<5>  | a<13>  | a<4>  | a<3>  | a<0>  | a<12>  | use_freezer/next_state_FSM_FFd1  | use_freezer/next_state_FSM_FFd3  | activate_n_sync<1>  | $OpTx$FX_SC$586
INPUTMC | 7 | 6 | 5 | 2 | 6 | 4 | 1 | 2 | 7 | 2 | 4 | 6 | 9 | 3 | 2
INPUTP | 11 | 22 | 23 | 56 | 18 | 8 | 6 | 21 | 2 | 59 | 68 | 19
EQ | 11 | 
   use_freezer/next_state_FSM_FFd2.D = reset_n_sync<1> & use_freezer/next_state_FSM_FFd2 & 
	!$OpTx$FX_DC$580
	# a<14> & a<15> & rw & a<11> & a<6> & a<5> & 
	a<13> & a<4> & a<3> & a<0> & a<12> & reset_n_sync<1> & 
	!use_freezer/next_state_FSM_FFd1 & use_freezer/next_state_FSM_FFd3 & 
	!activate_n_sync<1> & $OpTx$FX_SC$586
	# a<14> & a<15> & rw & a<11> & a<6> & a<5> & 
	a<13> & a<4> & a<3> & a<0> & a<12> & reset_n_sync<1> & 
	!use_freezer/next_state_FSM_FFd1 & use_freezer/next_state_FSM_FFd2 & 
	!activate_n_sync<1> & $OpTx$FX_SC$586;
   !use_freezer/next_state_FSM_FFd2.CLK = phi2short;	// GCK
GLOBALS | 1 | 2 | phi2short

MACROCELL | 6 | 9 | activate_n_sync<1>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 3 | 2 | 1 | 2 | 4 | 2 | 6
INPUTS | 1 | activate_n_sync<0>
INPUTMC | 1 | 6 | 10
EQ | 2 | 
   activate_n_sync<1>.D = activate_n_sync<0>;
   !activate_n_sync<1>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 4 | reset_n_sync<2>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 2 | 6 | 8 | 6 | 3
INPUTS | 1 | reset_n_sync<1>
INPUTMC | 1 | 6 | 5
EQ | 2 | 
   reset_n_sync<2>.D = reset_n_sync<1>;
   !reset_n_sync<2>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 10 | activate_n_sync<0>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 1 | 6 | 9
INPUTS | 1 | activate_n_in
INPUTP | 1 | 72
EQ | 2 | 
   activate_n_sync<0>.D = activate_n_in;
   !activate_n_sync<0>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 6 | reset_n_sync<0>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 1 | 6 | 5
INPUTS | 1 | reset_n_in
INPUTP | 1 | 160
EQ | 2 | 
   reset_n_sync<0>.D = reset_n_in;
   !reset_n_sync<0>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 6 | 3 | reset_n_sync<3>
ATTRIBUTES | 8553217 | 0
OUTPUTMC | 1 | 6 | 8
INPUTS | 1 | reset_n_sync<2>
INPUTMC | 1 | 6 | 4
EQ | 2 | 
   reset_n_sync<3>.D = reset_n_sync<2>;
   !reset_n_sync<3>.CLK = phi2;	// GCK
GLOBALS | 1 | 2 | phi2

MACROCELL | 5 | 11 | ram0_ce_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 12
INPUTS | 14 | phi2  | a<13>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$577  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<14>  | a<15>  | use_cartemu/cfg_mode<1>  | use_cartemu/cfg_mode<2>  | use_cartemu/oss_bank<0>  | use_cartemu/oss_bank<1>  | use_cartemu/N29/use_cartemu/N29_D2.EXP
INPUTMC | 10 | 3 | 17 | 7 | 15 | 1 | 17 | 1 | 15 | 6 | 7 | 7 | 7 | 7 | 6 | 4 | 14 | 4 | 13 | 5 | 10
INPUTP | 4 | 33 | 21 | 22 | 23
EXPORTS | 1 | 5 | 12
IMPORTS | 1 | 5 | 10
EQ | 29 | 
   !ram0_ce = !a<14> & phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !a<15> & phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & !a<13> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
;Imported pterms FB6_11
	# phi2 & oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !a<14> & !a<15> & phi2 & !a<13> & 
	use_freezer/state<1> & !use_freezer/state<2> & !use_freezer/state<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<14> & !a<15> & phi2 & !a<13> & 
	!use_freezer/state<1> & use_freezer/state<2> & !use_freezer/state<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2
	# a<14> & a<15> & !rw & !a<11> & phi2 & !a<13> & 
	a<12> & !use_freezer/state<1> & !use_freezer/state<2> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2;
    ram0_ce_OBUF.EXP  =  use_cartemu/cfg_mode<1>
	# use_cartemu/cfg_mode<2> & !use_cartemu/oss_bank<0> & 
	!use_cartemu/oss_bank<1>

MACROCELL | 3 | 14 | ram1_ce_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 10 | phi2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$577  | a<14>  | a<15>  | a<13>  | oldos_n
INPUTMC | 5 | 3 | 17 | 6 | 7 | 7 | 15 | 1 | 17 | 1 | 15
INPUTP | 5 | 33 | 22 | 23 | 21 | 69
EQ | 8 | 
   !ram1_ce = phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & $OpTx$FX_DC$577
	# a<14> & a<15> & phi2 & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2;

MACROCELL | 3 | 8 | ram_a_4_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 9 | a<4>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_freezer/use_status_as_ram_address<0>  | use_freezer/N24/use_freezer/N24_D2  | a<13>  | use_freezer/vector_a2  | use_freezer/N24/use_freezer/N24_D2.EXP
INPUTMC | 7 | 3 | 17 | 1 | 17 | 6 | 7 | 7 | 10 | 3 | 9 | 2 | 1 | 3 | 9
INPUTP | 2 | 2 | 21
IMPORTS | 1 | 3 | 9
EQ | 19 | 
   ram_a<4> = a<4> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# a<4> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<13> & a<4> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<4> & !use_freezer/use_status_as_ram_address<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/use_status_as_ram_address<0> & 
	use_freezer/vector_a2 & merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_freezer/N24/use_freezer/N24_D2
;Imported pterms FB4_10
	# a<14> & a<15> & a<13> & a<4> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<9> & !a<8> & !a<10> & a<4> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$FX_SC$591
	# !a<8> & !a<10> & a<4> & !dualpokey_n & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$FX_SC$591;

MACROCELL | 3 | 10 | ram_a_5_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 9 | a<5>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | a<13>  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/use_status_as_ram_address<0>  | dualpokey_n  | ram_a_6_OBUF.EXP
INPUTMC | 6 | 3 | 17 | 6 | 7 | 1 | 17 | 3 | 9 | 7 | 10 | 3 | 11
INPUTP | 3 | 6 | 21 | 57
IMPORTS | 1 | 3 | 11
EQ | 15 | 
   ram_a<5> = a<5> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# a<5> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<5> & a<13> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<5> & !use_freezer/use_status_as_ram_address<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/use_status_as_ram_address<0> & 
	!dualpokey_n & merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_freezer/N24/use_freezer/N24_D2
;Imported pterms FB4_12
	# a<14> & a<15> & a<5> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;

MACROCELL | 3 | 11 | ram_a_6_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 3 | 10
INPUTS | 10 | a<6>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_freezer/N24/use_freezer/N24_D2  | a<14>  | a<15>  | a<13>  | oldos_n  | a<5>
INPUTMC | 4 | 3 | 17 | 6 | 7 | 1 | 17 | 3 | 9
INPUTP | 6 | 8 | 22 | 23 | 21 | 69 | 6
EXPORTS | 1 | 3 | 10
EQ | 11 | 
   ram_a<6> = a<6> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<6> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# a<6> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<14> & a<15> & a<6> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;
    ram_a_6_OBUF.EXP  =  a<14> & a<15> & a<5> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2

MACROCELL | 3 | 13 | ram_a_7_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 9 | a<7>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_freezer/N24/use_freezer/N24_D2  | a<14>  | a<15>  | a<13>  | oldos_n
INPUTMC | 4 | 3 | 17 | 6 | 7 | 1 | 17 | 3 | 9
INPUTP | 5 | 11 | 22 | 23 | 21 | 69
EQ | 9 | 
   ram_a<7> = a<7> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<7> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# a<7> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<14> & a<15> & a<13> & a<7> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;

MACROCELL | 5 | 13 | ram_rom_a_12_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 10 | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$FX_SC$591  | a<12>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_cartemu/cfg_mode<0>  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$522  | use_cartemu/cfg_menu  | $OpTx$FX_DC$601.EXP  | ram_rom_a_13_OBUF.EXP
INPUTMC | 9 | 3 | 17 | 3 | 0 | 6 | 7 | 0 | 3 | 1 | 17 | 5 | 17 | 7 | 9 | 5 | 12 | 5 | 14
INPUTP | 1 | 19
IMPORTS | 2 | 5 | 12 | 5 | 14
EQ | 35 | 
   ram_rom_a<12> = merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_SC$591
	# a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !use_cartemu/cfg_mode<0> & a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# use_cartemu/cfg_menu & a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
;Imported pterms FB6_13
	# a<13> & a<12> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & !a<12> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_0 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# !use_cartemu/oss_bank<0> & !use_cartemu/oss_bank<1> & 
	a<12> & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
;Imported pterms FB6_15
	# a<14> & a<15> & a<13> & a<12> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	use_cartemu/oss_bank<0> & !a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2;

MACROCELL | 5 | 14 | ram_rom_a_13_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 13
INPUTS | 16 | $OpTx$FX_DC$538  | a<13>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_cartemu/cfg_menu  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$608  | a<14>  | a<15>  | a<12>  | oldos_n  | use_cartemu/cfg_mode<0>  | use_cartemu/oss_bank<0>  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | $OpTx$FX_DC$522  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2.EXP
INPUTMC | 11 | 3 | 15 | 3 | 17 | 6 | 7 | 7 | 9 | 1 | 17 | 6 | 16 | 0 | 3 | 4 | 14 | 1 | 9 | 5 | 17 | 5 | 15
INPUTP | 5 | 21 | 22 | 23 | 19 | 69
EXPORTS | 1 | 5 | 13
IMPORTS | 1 | 5 | 15
EQ | 31 | 
   ram_rom_a<13> = $OpTx$FX_DC$538
	# a<13> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !use_cartemu/cfg_menu & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & $OpTx$FX_DC$608
;Imported pterms FB6_16
	# a<13> & use_freezer/rom_bank_0 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_1 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !use_cartemu/cfg_menu & use_cartemu/cfg_bank<0> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & use_cartemu/N29/use_cartemu/N29_D2
	# !use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	a<13> & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	use_cartemu/oss_bank<1> & !a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2;
    ram_rom_a_13_OBUF.EXP  =  a<14> & a<15> & a<13> & a<12> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	use_cartemu/oss_bank<0> & !a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2

MACROCELL | 5 | 16 | ram_rom_a_14_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 15
INPUTS | 17 | $OpTx$FX_DC$538  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$571  | use_pia/pia_ddrb<2>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<14>  | a<15>  | a<11>  | a<9>  | a<8>  | a<10>  | a<13>  | a<12>  | flash_we_n  | cartemu_enable_n  | $OpTx$FX_DC$522.EXP
INPUTMC | 7 | 3 | 15 | 3 | 17 | 1 | 17 | 1 | 16 | 4 | 10 | 6 | 7 | 5 | 17
INPUTP | 10 | 22 | 23 | 18 | 15 | 13 | 17 | 21 | 19 | 29 | 12
EXPORTS | 1 | 5 | 15
IMPORTS | 1 | 5 | 17
EQ | 16 | 
   ram_rom_a<14> = $OpTx$FX_DC$538
	# !use_pia/pia_ddrb<2> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$571
;Imported pterms FB6_18
	# use_pia/pia_portb<2> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<13> & use_freezer/rom_bank_1 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_2 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2;
    ram_rom_a_14_OBUF.EXP  =  a<14> & a<15> & !a<11> & !a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !flash_we_n
	# a<14> & a<15> & !a<11> & !a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !cartemu_enable_n

MACROCELL | 3 | 1 | ram_rom_a_15_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 11 | $OpTx$FX_DC$538  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2  | use_pia/pia_ddrb<3>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_pia/pia_portb<3>  | a<13>  | use_freezer/ram_bank_3  | use_freezer/N24/use_freezer/N24_D2  | $OpTx$FX_SC$591.EXP
INPUTMC | 10 | 3 | 15 | 3 | 17 | 1 | 17 | 1 | 14 | 4 | 9 | 6 | 7 | 4 | 3 | 2 | 13 | 3 | 9 | 3 | 0
INPUTP | 1 | 21
IMPORTS | 1 | 3 | 0
EQ | 13 | 
   ram_rom_a<15> = $OpTx$FX_DC$538
	# !use_pia/pia_ddrb<3> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# use_pia/pia_portb<3> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & 
	!use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2
	# !a<13> & use_freezer/ram_bank_3 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
;Imported pterms FB4_1
	# a<13> & use_freezer/rom_bank_2 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2;

MACROCELL | 3 | 4 | ram_rom_a_16_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 3 | 5
INPUTS | 13 | $OpTx$FX_DC$538  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2  | use_pia/pia_ddrb<5>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_freezer/rom_bank_4  | use_freezer/N24/use_freezer/N24_D2  | a<14>  | a<15>  | a<13>  | oldos_n  | $OpTx$FX_DC$521.EXP
INPUTMC | 9 | 3 | 15 | 3 | 17 | 1 | 17 | 1 | 13 | 4 | 7 | 6 | 7 | 4 | 16 | 3 | 9 | 3 | 3
INPUTP | 4 | 22 | 23 | 21 | 69
EXPORTS | 1 | 3 | 5
IMPORTS | 1 | 3 | 3
EQ | 17 | 
   ram_rom_a<16> = $OpTx$FX_DC$538
	# !use_pia/pia_ddrb<5> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & 
	!use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2
;Imported pterms FB4_4
	# use_pia/pia_portb<5> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<13> & use_freezer/rom_bank_3 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_4 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2;
    ram_rom_a_16_OBUF.EXP  =  use_freezer/rom_bank_4 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2

MACROCELL | 3 | 5 | ram_rom_a_17_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 10 | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$FX_SC$591  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2  | use_pia/pia_ddrb<6>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_pia/pia_portb<6>  | a<13>  | use_freezer/N24/use_freezer/N24_D2  | ram_rom_a_16_OBUF.EXP
INPUTMC | 9 | 3 | 17 | 3 | 0 | 1 | 17 | 1 | 12 | 4 | 6 | 6 | 7 | 6 | 12 | 3 | 9 | 3 | 4
INPUTP | 1 | 21
IMPORTS | 1 | 3 | 4
EQ | 16 | 
   ram_rom_a<17> = merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_SC$591
	# !a<13> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !use_pia/pia_ddrb<6> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# use_pia/pia_portb<6> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & 
	!use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2
;Imported pterms FB4_5
	# use_freezer/rom_bank_4 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;

MACROCELL | 3 | 7 | ram_rom_a_18_OBUF
ATTRIBUTES | 264961 | 0
INPUTS | 9 | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$FX_SC$591  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$540  | use_cartemu/cfg_menu  | use_pia/pia_ddrb<7>  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_pia/pia_portb<7>  | $OpTx$FX_DC$499.EXP
INPUTMC | 9 | 3 | 17 | 3 | 0 | 1 | 17 | 6 | 17 | 7 | 9 | 4 | 5 | 6 | 7 | 6 | 11 | 3 | 6
IMPORTS | 1 | 3 | 6
EQ | 18 | 
   ram_rom_a<18> = merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_SC$591
	# use_cartemu/cfg_menu & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# !use_pia/pia_ddrb<7> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# use_pia/pia_portb<7> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & $OpTx$FX_DC$540
;Imported pterms FB4_7
	# !a<13> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# use_freezer/rom_bank_5 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;

MACROCELL | 5 | 7 | ram_rom_oe_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 8
INPUTS | 10 | rw  | phi2  | a<15>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$577  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<13>  | oldos_n
INPUTMC | 5 | 3 | 17 | 7 | 15 | 1 | 17 | 1 | 15 | 6 | 7
INPUTP | 5 | 56 | 33 | 23 | 21 | 69
EXPORTS | 1 | 5 | 8
EQ | 13 | 
   !ram_rom_oe = rw & phi2;
    ram_rom_oe_OBUF.EXP  =  !a<15> & phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & !a<13> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2

MACROCELL | 5 | 5 | ram_rom_we_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 6
INPUTS | 14 | a<14>  | a<15>  | a<13>  | oldos_n  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>  | a<11>  | a<9>  | a<8>  | a<10>  | a<12>  | EXP16_.EXP
INPUTMC | 5 | 3 | 17 | 6 | 1 | 6 | 0 | 6 | 2 | 5 | 4
INPUTP | 9 | 22 | 23 | 21 | 69 | 18 | 15 | 13 | 17 | 19
EXPORTS | 1 | 5 | 6
IMPORTS | 1 | 5 | 4
EQ | 14 | 
   !ram_rom_we = ;Imported pterms FB6_5
	  !rw & phi2short;
    ram_rom_we_OBUF.EXP  =  a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<14> & !a<15> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>
	# !a<14> & !a<15> & !use_freezer/state<1> & 
	use_freezer/state<2> & !use_freezer/state<0>
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !use_freezer/state<1> & 
	use_freezer/state<2>
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>

MACROCELL | 5 | 8 | rom0_ce_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 5 | 9
INPUTS | 17 | a<14>  | phi2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$577  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<15>  | use_cartemu/cfg_enable  | a<13>  | use_cartemu/N29/use_cartemu/N29_D2  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_menu  | use_cartemu/cfg_mode<2>  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | use_cartemu/cfg_mode<1>  | ram_rom_oe_OBUF.EXP
INPUTMC | 13 | 3 | 17 | 7 | 15 | 1 | 17 | 1 | 15 | 6 | 7 | 0 | 1 | 5 | 10 | 0 | 3 | 7 | 9 | 7 | 6 | 1 | 9 | 7 | 7 | 5 | 7
INPUTP | 4 | 22 | 33 | 23 | 21
EXPORTS | 1 | 5 | 9
IMPORTS | 1 | 5 | 7
EQ | 28 | 
   !rom0_ce = !a<14> & phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
;Imported pterms FB6_8
	# !a<15> & phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & !a<13> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# phi2 & oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2;
    rom0_ce_OBUF.EXP  =  !a<14> & a<15> & use_cartemu/cfg_enable & a<13> & 
	!use_cartemu/N29/use_cartemu/N29_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_menu & use_cartemu/cfg_enable & 
	!use_cartemu/N29/use_cartemu/N29_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_enable & a<13> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & use_cartemu/cfg_enable & a<13> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2

MACROCELL | 3 | 16 | rom1_ce_OBUF
ATTRIBUTES | 264961 | 0
OUTPUTMC | 1 | 3 | 17
INPUTS | 21 | phi2  | a<13>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/N24/use_freezer/N24_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | $OpTx$FX_DC$577  | a<14>  | a<15>  | rw  | oldos_n  | a<11>  | a<9>  | a<8>  | a<10>  | a<12>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>  | $OpTx$FX_DC$538.EXP
INPUTMC | 10 | 3 | 17 | 3 | 9 | 7 | 15 | 1 | 17 | 6 | 7 | 1 | 15 | 6 | 1 | 6 | 0 | 6 | 2 | 3 | 15
INPUTP | 11 | 33 | 21 | 22 | 23 | 56 | 69 | 18 | 15 | 13 | 17 | 19
EXPORTS | 1 | 3 | 17
IMPORTS | 1 | 3 | 15
EQ | 17 | 
   !rom1_ce = phi2 & a<13> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & $OpTx$FX_DC$577
	# phi2 & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<14> & a<15> & rw & phi2 & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
;Imported pterms FB4_16
	# a<14> & a<15> & phi2 & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2;
    rom1_ce_OBUF.EXP  =  a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>

MACROCELL | 7 | 16 | N0
ATTRIBUTES | 265985 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 6 | N0/N0_TRST  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | use_cartemu/N4/use_cartemu/N4_D2
INPUTMC | 6 | 5 | 6 | 7 | 6 | 0 | 3 | 7 | 7 | 1 | 9 | 1 | 0
EXPORTS | 1 | 7 | 15
EQ | 5 | 
   refresh = Gnd;
   refresh.OE = N0/N0_TRST;
    N0.EXP  =  !use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2

MACROCELL | 5 | 15 | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 44 | 0 | 2 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 2 | 11 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 1 | 10 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 14 | 4 | 13 | 4 | 12 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 1 | 4 | 11 | 1 | 11 | 0 | 0 | 0 | 4 | 2 | 17 | 0 | 8 | 0 | 16 | 2 | 0 | 2 | 7 | 5 | 14
INPUTS | 16 | a<13>  | use_freezer/rom_bank_0  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/ram_bank_1  | use_cartemu/cfg_menu  | use_cartemu/cfg_bank<0>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_cartemu/N29/use_cartemu/N29_D2  | use_cartemu/cfg_mode<0>  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | $OpTx$FX_DC$522  | use_cartemu/oss_bank<1>  | a<12>  | ram_rom_a_14_OBUF.EXP
INPUTMC | 14 | 7 | 13 | 3 | 17 | 3 | 9 | 2 | 15 | 7 | 9 | 0 | 13 | 2 | 2 | 1 | 17 | 5 | 10 | 0 | 3 | 1 | 9 | 5 | 17 | 4 | 13 | 5 | 16
INPUTP | 2 | 21 | 19
EXPORTS | 1 | 5 | 14
IMPORTS | 1 | 5 | 16
EQ | 22 | 
   use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 = ;Imported pterms FB6_17
	  a<14> & a<15> & !a<11> & !a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !flash_we_n
	# a<14> & a<15> & !a<11> & !a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !cartemu_enable_n;
    use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2.EXP  =  a<13> & use_freezer/rom_bank_0 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_1 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !use_cartemu/cfg_menu & use_cartemu/cfg_bank<0> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & use_cartemu/N29/use_cartemu/N29_D2
	# !use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	a<13> & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/cfg_menu & 
	use_cartemu/oss_bank<1> & !a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & $OpTx$FX_DC$522 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2

MACROCELL | 3 | 17 | merged_out_dout_or0000/merged_out_dout_or0000_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 40 | 0 | 8 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 2 | 11 | 0 | 15 | 5 | 11 | 3 | 14 | 3 | 8 | 3 | 10 | 3 | 11 | 3 | 13 | 5 | 13 | 5 | 14 | 5 | 16 | 3 | 1 | 3 | 4 | 3 | 5 | 3 | 7 | 5 | 8 | 3 | 16 | 3 | 15 | 5 | 6 | 0 | 7 | 0 | 9 | 0 | 13 | 2 | 7 | 3 | 0 | 3 | 3 | 3 | 6 | 3 | 9 | 5 | 5 | 5 | 7 | 5 | 10 | 5 | 12 | 5 | 15 | 5 | 17
INPUTS | 14 | freezer_mem_dout<5>/freezer_mem_dout<5>_D2  | a<14>  | a<15>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>  | rw  | a<11>  | a<13>  | a<12>  | a<9>  | a<8>  | a<10>  | rom1_ce_OBUF.EXP
INPUTMC | 5 | 3 | 12 | 6 | 1 | 6 | 0 | 6 | 2 | 3 | 16
INPUTP | 9 | 22 | 23 | 56 | 18 | 21 | 19 | 15 | 13 | 17
IMPORTS | 1 | 3 | 16
EQ | 14 | 
   merged_out_dout_or0000/merged_out_dout_or0000_D2 = freezer_mem_dout<5>/freezer_mem_dout<5>_D2
	# !a<14> & !a<15> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>
	# !a<14> & !a<15> & !use_freezer/state<1> & 
	use_freezer/state<2> & !use_freezer/state<0>
	# a<14> & a<15> & !rw & !a<11> & !a<13> & a<12> & 
	!use_freezer/state<1> & !use_freezer/state<2>
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !use_freezer/state<1> & 
	use_freezer/state<2>
;Imported pterms FB4_17
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>;

MACROCELL | 3 | 12 | freezer_mem_dout<5>/freezer_mem_dout<5>_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 5 | 0 | 8 | 2 | 8 | 0 | 15 | 3 | 17 | 5 | 6
INPUTS | 18 | a<14>  | a<15>  | rw  | a<11>  | a<9>  | a<8>  | a<10>  | a<6>  | a<5>  | a<13>  | a<4>  | a<7>  | a<3>  | a<0>  | a<12>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>
INPUTMC | 3 | 6 | 1 | 6 | 0 | 6 | 2
INPUTP | 15 | 22 | 23 | 56 | 18 | 15 | 13 | 17 | 8 | 6 | 21 | 2 | 11 | 59 | 68 | 19
EQ | 8 | 
   freezer_mem_dout<5>/freezer_mem_dout<5>_D2 = a<14> & a<15> & rw & a<11> & a<9> & a<8> & 
	a<10> & a<6> & a<5> & a<13> & a<4> & a<7> & a<3> & 
	a<0> & a<12> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>
	# a<14> & a<15> & rw & a<11> & a<9> & a<8> & 
	a<10> & a<6> & a<5> & a<13> & a<4> & a<7> & a<3> & 
	a<0> & a<12> & !use_freezer/state<1> & 
	!use_freezer/state<2> & use_freezer/state<0>;

MACROCELL | 7 | 17 | use_cartemu/N50/use_cartemu/N50_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 1 | 0 | 7
INPUTS | 12 | a<6>  | a<5>  | a<1>  | a<2>  | use_cartemu/cfg_bank<0>  | a<4>  | a<0>  | use_cartemu/cfg_enable  | use_cartemu/cfg_write_enable  | use_cartemu/cfg_sram_enable  | use_cartemu/cfg_mode<0>  | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2.EXP
INPUTMC | 6 | 0 | 13 | 0 | 1 | 0 | 17 | 7 | 8 | 0 | 3 | 7 | 0
INPUTP | 6 | 8 | 6 | 79 | 58 | 2 | 68
IMPORTS | 1 | 7 | 0
EQ | 19 | 
   use_cartemu/N50/use_cartemu/N50_D2 = !a<6> & !a<5> & use_cartemu/cfg_mode<0> & !a<1> & 
	a<2> & a<4> & !a<0>
	# !a<6> & !a<5> & a<1> & 
	use_cartemu/cfg_sram_enable & !a<2> & a<4> & a<0>
	# !a<6> & !a<5> & !a<1> & use_cartemu/cfg_enable & 
	!a<2> & a<4> & a<0>
	# !a<6> & !a<5> & !a<1> & a<2> & a<4> & 
	use_cartemu/cfg_write_enable & a<0>
	# !a<6> & !a<5> & !a<1> & !a<2> & 
	use_cartemu/cfg_bank<0> & a<4> & !a<0>
;Imported pterms FB8_1
	# !a<6> & !a<5> & a<1> & use_cartemu/cfg_usdx<0> & 
	a<2> & a<4> & !a<0>
	# !a<6> & !a<5> & a<1> & !a<2> & a<4> & 
	use_cartemu/cfg_sram_bank<0> & !a<0>
	# a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<0> & 
	!a<2> & !a<4> & !a<0> & use_cartemu/usdx_bank<0>
	# a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<1> & 
	!a<2> & !a<4> & !a<0> & use_cartemu/usdx_bank<0>;

MACROCELL | 3 | 6 | $OpTx$FX_DC$499
ATTRIBUTES | 133889 | 0
OUTPUTMC | 27 | 0 | 10 | 0 | 11 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 0 | 9 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 0 | 0 | 0 | 4 | 2 | 17 | 0 | 2 | 0 | 16 | 2 | 0 | 3 | 7
INPUTS | 10 | a<6>  | a<5>  | a<4>  | a<13>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/rom_bank_5  | a<14>  | a<15>  | oldos_n
INPUTMC | 3 | 3 | 17 | 3 | 9 | 4 | 15
INPUTP | 7 | 8 | 6 | 2 | 21 | 22 | 23 | 69
EXPORTS | 1 | 3 | 7
EQ | 7 | 
   $OpTx$FX_DC$499 = !a<6> & !a<5> & a<4>;
    $OpTx$FX_DC$499.EXP  =  !a<13> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# use_freezer/rom_bank_5 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2

MACROCELL | 2 | 3 | use_cartemu/N97/use_cartemu/N97_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 12 | 0 | 10 | 0 | 11 | 2 | 11 | 1 | 10 | 4 | 12 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 1 | 4 | 11 | 1 | 11 | 2 | 17
INPUTS | 10 | a<6>  | a<5>  | a<1>  | use_cartemu/cfg_usdx<1>  | a<2>  | a<4>  | a<7>  | a<3>  | a<0>  | use_cartemu/cfg_usdx<0>
INPUTMC | 2 | 7 | 3 | 7 | 4
INPUTP | 8 | 8 | 6 | 79 | 58 | 2 | 11 | 59 | 68
EQ | 4 | 
   use_cartemu/N97/use_cartemu/N97_D2 = a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<0> & 
	!a<2> & !a<4> & a<7> & !a<3> & !a<0>
	# a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<1> & 
	!a<2> & !a<4> & a<7> & !a<3> & !a<0>;

MACROCELL | 2 | 0 | $OpTx$FX_DC$508
ATTRIBUTES | 133889 | 0
OUTPUTMC | 12 | 0 | 1 | 0 | 17 | 4 | 14 | 4 | 13 | 7 | 2 | 4 | 0 | 7 | 1 | 2 | 0 | 2 | 17 | 0 | 0 | 0 | 2 | 0 | 16
INPUTS | 12 | a<1>  | a<7>  | a<3>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | a<2>  | a<6>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | $OpTx$FX_DC$508  | use_freezer/vector_a2.EXP
INPUTMC | 7 | 5 | 15 | 3 | 6 | 7 | 6 | 0 | 3 | 7 | 7 | 2 | 0 | 2 | 1
INPUTP | 5 | 79 | 11 | 59 | 58 | 8
EXPORTS | 1 | 2 | 17
IMPORTS | 1 | 2 | 1
EQ | 15 | 
   $OpTx$FX_DC$508 = ;Imported pterms FB3_2
	  !a<6> & !a<5> & !a<4>;
    $OpTx$FX_DC$508.EXP  =  !a<1> & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !a<2> & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508

MACROCELL | 0 | 2 | use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 9 | 7 | 4 | 7 | 3 | 6 | 15 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 6 | 14 | 0 | 1
INPUTS | 16 | rw  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | a<1>  | use_cartemu/cfg_enable  | a<2>  | a<7>  | a<3>  | a<0>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | d<0>.PIN  | $OpTx$FX_DC$508  | use_cartemu/cfg_mode<1>  | use_cartemu/cfg_mode<0>.EXP
INPUTMC | 9 | 7 | 6 | 0 | 3 | 0 | 1 | 6 | 5 | 5 | 15 | 3 | 6 | 2 | 0 | 7 | 7 | 0 | 3
INPUTP | 7 | 56 | 79 | 58 | 11 | 59 | 68 | 24
EXPORTS | 1 | 0 | 1
IMPORTS | 1 | 0 | 3
EQ | 23 | 
   use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 = ;Imported pterms FB1_4
	  !rw & a<1> & !a<2> & a<7> & !a<3> & !a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;
    use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2.EXP  =  !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & use_cartemu/cfg_mode<2> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & use_cartemu/cfg_enable & !a<2> & 
	a<7> & !d<0>.PIN & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508

MACROCELL | 0 | 4 | $OpTx$FX_DC$510
ATTRIBUTES | 133889 | 0
OUTPUTMC | 6 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5
INPUTS | 13 | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | a<6>  | rw  | a<1>  | a<2>  | a<3>  | a<0>  | $OpTx$FX_DC$499
INPUTMC | 6 | 7 | 6 | 0 | 3 | 7 | 7 | 6 | 5 | 5 | 15 | 3 | 6
INPUTP | 7 | 11 | 8 | 56 | 79 | 58 | 59 | 68
EQ | 9 | 
   $OpTx$FX_DC$510 = use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# !rw & !a<1> & !a<2> & a<7> & !a<3> & !a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499;

MACROCELL | 1 | 9 | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 9 | 7 | 14 | 5 | 12 | 5 | 8 | 7 | 15 | 1 | 0 | 5 | 9 | 5 | 14 | 5 | 15 | 7 | 16
INPUTS | 4 | use_cartemu/cfg_usdx<0>  | use_cartemu/cfg_usdx<1>  | use_cartemu/usdx_ctl<0>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2
INPUTMC | 4 | 7 | 4 | 7 | 3 | 1 | 11 | 2 | 2
EQ | 3 | 
   use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 = !use_cartemu/cfg_usdx<0> & !use_cartemu/cfg_usdx<1>
	# !use_cartemu/usdx_ctl<0> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2;

MACROCELL | 2 | 2 | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 12 | 7 | 14 | 6 | 16 | 1 | 9 | 7 | 15 | 5 | 9 | 1 | 14 | 1 | 13 | 1 | 16 | 1 | 12 | 6 | 17 | 1 | 15 | 5 | 15
INPUTS | 3 | use_cartemu/cfg_usdx<1>  | use_cartemu/usdx_ctl<1>  | use_cartemu/cfg_usdx<0>
INPUTMC | 3 | 7 | 3 | 1 | 10 | 7 | 4
EQ | 2 | 
   use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 = use_cartemu/cfg_usdx<0> & !use_cartemu/usdx_ctl<1>
	# use_cartemu/cfg_usdx<1> & !use_cartemu/usdx_ctl<1>;

MACROCELL | 3 | 3 | $OpTx$FX_DC$521
ATTRIBUTES | 133889 | 0
OUTPUTMC | 13 | 7 | 14 | 7 | 2 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 4 | 0 | 7 | 1 | 4 | 1 | 3 | 4
INPUTS | 12 | a<14>  | a<15>  | a<11>  | a<13>  | a<7>  | a<12>  | use_pia/pia_portb<5>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | use_freezer/rom_bank_3  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/ram_bank_4
INPUTMC | 6 | 6 | 13 | 3 | 17 | 6 | 7 | 4 | 17 | 3 | 9 | 2 | 12
INPUTP | 6 | 22 | 23 | 18 | 21 | 11 | 19
EXPORTS | 1 | 3 | 4
EQ | 7 | 
   $OpTx$FX_DC$521 = a<14> & a<15> & !a<11> & !a<13> & !a<7> & a<12>;
    $OpTx$FX_DC$521.EXP  =  use_pia/pia_portb<5> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<13> & use_freezer/rom_bank_3 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_4 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2

MACROCELL | 5 | 12 | $OpTx$FX_DC$601
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 7 | 14 | 5 | 13
INPUTS | 10 | a<13>  | a<12>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/ram_bank_0  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | use_cartemu/oss_bank<0>  | use_cartemu/oss_bank<1>  | ram0_ce_OBUF.EXP
INPUTMC | 8 | 3 | 17 | 3 | 9 | 2 | 16 | 1 | 9 | 1 | 17 | 4 | 14 | 4 | 13 | 5 | 11
INPUTP | 2 | 21 | 19
EXPORTS | 1 | 5 | 13
IMPORTS | 1 | 5 | 11
EQ | 17 | 
   $OpTx$FX_DC$601 = ;Imported pterms FB6_12
	  use_cartemu/cfg_mode<1>
	# use_cartemu/cfg_mode<2> & !use_cartemu/oss_bank<0> & 
	!use_cartemu/oss_bank<1>;
    $OpTx$FX_DC$601.EXP  =  a<13> & a<12> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & !a<12> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_0 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<12> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
	# !use_cartemu/oss_bank<0> & !use_cartemu/oss_bank<1> & 
	a<12> & !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2

MACROCELL | 5 | 17 | $OpTx$FX_DC$522
ATTRIBUTES | 133889 | 0
OUTPUTMC | 7 | 4 | 14 | 4 | 13 | 5 | 13 | 5 | 10 | 5 | 14 | 5 | 15 | 5 | 16
INPUTS | 9 | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<1>  | use_pia/pia_portb<2>  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<13>  | use_freezer/rom_bank_1  | use_freezer/N24/use_freezer/N24_D2  | use_freezer/ram_bank_2
INPUTMC | 8 | 7 | 6 | 7 | 7 | 4 | 4 | 3 | 17 | 6 | 7 | 7 | 12 | 3 | 9 | 2 | 14
INPUTP | 1 | 21
EXPORTS | 1 | 5 | 16
EQ | 7 | 
   $OpTx$FX_DC$522 = use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<1>;
    $OpTx$FX_DC$522.EXP  =  use_pia/pia_portb<2> & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# a<13> & use_freezer/rom_bank_1 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# !a<13> & use_freezer/ram_bank_2 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2

MACROCELL | 4 | 0 | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 6 | 7 | 2 | 7 | 10 | 2 | 7 | 2 | 4 | 7 | 1 | 4 | 1
INPUTS | 5 | a<9>  | a<8>  | a<10>  | $OpTx$FX_DC$508  | $OpTx$FX_DC$521
INPUTMC | 2 | 2 | 0 | 3 | 3
INPUTP | 3 | 15 | 13 | 17
EQ | 2 | 
   use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 = a<9> & a<8> & a<10> & $OpTx$FX_DC$508 & 
	$OpTx$FX_DC$521;

MACROCELL | 3 | 2 | $OpTx$FX_SC$586
ATTRIBUTES | 133889 | 0
OUTPUTMC | 8 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6
INPUTS | 4 | a<9>  | a<8>  | a<10>  | a<7>
INPUTP | 4 | 15 | 13 | 17 | 11
EQ | 1 | 
   $OpTx$FX_SC$586 = a<9> & a<8> & a<10> & a<7>;

MACROCELL | 7 | 1 | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 7 | 4 | 10 | 4 | 9 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 7 | 0
INPUTS | 12 | reset_n_sync<1>  | rw  | a<9>  | a<8>  | a<1>  | a<2>  | a<3>  | a<0>  | use_pia/pia_crb2  | $OpTx$FX_DC$508  | $OpTx$FX_DC$521  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
INPUTMC | 5 | 6 | 5 | 7 | 2 | 2 | 0 | 3 | 3 | 4 | 0
INPUTP | 7 | 56 | 15 | 13 | 79 | 58 | 59 | 68
EXPORTS | 1 | 7 | 0
EQ | 7 | 
   use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 = !reset_n_sync<1>
	# !rw & a<9> & a<8> & !a<1> & !a<2> & !a<3> & a<0> & 
	!use_pia/pia_crb2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2;
    use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2.EXP  =  !rw & a<9> & a<8> & !a<1> & !a<2> & !a<3> & a<0> & 
	use_pia/pia_crb2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2

MACROCELL | 7 | 0 | use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 7 | 4 | 4 | 4 | 3 | 4 | 2 | 6 | 13 | 6 | 12 | 6 | 11 | 7 | 17
INPUTS | 12 | reset_n_sync<1>  | a<6>  | a<5>  | a<1>  | use_cartemu/cfg_usdx<0>  | a<2>  | a<4>  | a<0>  | use_cartemu/cfg_sram_bank<0>  | use_cartemu/usdx_bank<0>  | use_cartemu/cfg_usdx<1>  | use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2.EXP
INPUTMC | 6 | 6 | 5 | 7 | 4 | 6 | 15 | 4 | 12 | 7 | 3 | 7 | 1
INPUTP | 6 | 8 | 6 | 79 | 58 | 2 | 68
EXPORTS | 1 | 7 | 17
IMPORTS | 1 | 7 | 1
EQ | 13 | 
   use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 = !reset_n_sync<1>
;Imported pterms FB8_2
	# !rw & a<9> & a<8> & !a<1> & !a<2> & !a<3> & a<0> & 
	use_pia/pia_crb2 & $OpTx$FX_DC$508 & $OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2;
    use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2.EXP  =  !a<6> & !a<5> & a<1> & use_cartemu/cfg_usdx<0> & 
	a<2> & a<4> & !a<0>
	# !a<6> & !a<5> & a<1> & !a<2> & a<4> & 
	use_cartemu/cfg_sram_bank<0> & !a<0>
	# a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<0> & 
	!a<2> & !a<4> & !a<0> & use_cartemu/usdx_bank<0>
	# a<6> & a<5> & !a<1> & use_cartemu/cfg_usdx<1> & 
	!a<2> & !a<4> & !a<0> & use_cartemu/usdx_bank<0>

MACROCELL | 4 | 1 | $OpTx$FX_DC$580
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 2 | 7 | 2 | 6
INPUTS | 7 | a<9>  | a<8>  | a<10>  | a<6>  | a<4>  | $OpTx$FX_DC$521  | use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2
INPUTMC | 2 | 3 | 3 | 4 | 0
INPUTP | 5 | 15 | 13 | 17 | 8 | 2
EQ | 3 | 
   $OpTx$FX_DC$580 = a<9> & a<8> & a<10> & !a<6> & !a<4> & 
	$OpTx$FX_DC$521 & 
	!use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2;

MACROCELL | 7 | 15 | $OpTx$INV$490
ATTRIBUTES | 133889 | 0
OUTPUTMC | 9 | 5 | 11 | 3 | 14 | 5 | 8 | 3 | 16 | 1 | 17 | 1 | 16 | 3 | 15 | 5 | 7 | 5 | 10
INPUTS | 11 | use_cartemu/cfg_menu  | use_cartemu/cfg_usdx<0>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/cfg_usdx<1>  | use_cartemu/cfg_source_ram  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | N0.EXP
INPUTMC | 11 | 7 | 9 | 7 | 4 | 2 | 2 | 1 | 0 | 7 | 3 | 7 | 5 | 7 | 6 | 0 | 3 | 7 | 7 | 1 | 9 | 7 | 16
IMPORTS | 1 | 7 | 16
EQ | 14 | 
   $OpTx$INV$490 = use_cartemu/cfg_menu
	# !use_cartemu/cfg_usdx<0> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/cfg_usdx<1> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_source_ram & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2
;Imported pterms FB8_17
	# !use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 1 | 0 | use_cartemu/N4/use_cartemu/N4_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 13 | 7 | 15 | 1 | 17 | 5 | 9 | 5 | 10 | 1 | 14 | 1 | 13 | 1 | 16 | 1 | 12 | 6 | 17 | 1 | 15 | 6 | 16 | 1 | 0 | 7 | 16
INPUTS | 10 | a<14>  | a<15>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<13>  | use_cartemu/cfg_sram_enable  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | rw  | use_cartemu/N4/use_cartemu/N4_D2
INPUTMC | 6 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 8 | 1 | 9 | 1 | 0
INPUTP | 4 | 22 | 23 | 21 | 56
EXPORTS | 1 | 1 | 17
EQ | 10 | 
   use_cartemu/N4/use_cartemu/N4_D2 = !a<14> & a<15> & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<13> & 
	use_cartemu/cfg_sram_enable & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2;
    use_cartemu/N4/use_cartemu/N4_D2.EXP  =  !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2

MACROCELL | 1 | 17 | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 20 | 5 | 11 | 3 | 14 | 3 | 8 | 3 | 10 | 3 | 11 | 3 | 13 | 5 | 13 | 5 | 14 | 5 | 16 | 3 | 1 | 3 | 4 | 3 | 5 | 3 | 7 | 5 | 8 | 3 | 16 | 3 | 15 | 5 | 7 | 5 | 10 | 5 | 12 | 5 | 15
INPUTS | 10 | use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2  | rw  | use_cartemu/cfg_menu  | $OpTx$INV$490  | $OpTx$FX_DC$577  | flash_we_n  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/cfg_write_enable  | use_cartemu/N4/use_cartemu/N4_D2.EXP  | $OpTx$FX_DC$571.EXP
INPUTMC | 8 | 5 | 9 | 7 | 9 | 7 | 15 | 1 | 15 | 1 | 0 | 0 | 17 | 1 | 0 | 1 | 16
INPUTP | 2 | 56 | 29
IMPORTS | 2 | 1 | 0 | 1 | 16
EQ | 20 | 
   use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 = 
	!use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2
	# !rw & use_cartemu/cfg_menu
	# !$OpTx$INV$490 & $OpTx$FX_DC$577
	# !rw & !use_cartemu/cfg_write_enable & 
	!use_cartemu/N4/use_cartemu/N4_D2
	# !rw & flash_we_n & 
	!use_cartemu/N4/use_cartemu/N4_D2
;Imported pterms FB2_1
	# !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !use_cartemu/cfg_mode<1> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 & !use_cartemu/N4/use_cartemu/N4_D2
;Imported pterms FB2_17
	# !$OpTx$INV$490 & 
	!use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 & 
	!use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 & !$OpTx$FX_DC$571 & 
	!use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 & $OpTx$FX_DC$540;

MACROCELL | 5 | 9 | use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 3 | 1 | 17 | 5 | 6 | 5 | 10
INPUTS | 11 | use_cartemu/cfg_menu  | use_cartemu/N4/use_cartemu/N4_D2  | a<14>  | a<15>  | a<13>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2  | use_cartemu/cfg_mode<0>  | use_cartemu/oss_bank<0>  | use_cartemu/oss_bank<1>  | rom0_ce_OBUF.EXP
INPUTMC | 8 | 7 | 9 | 1 | 0 | 2 | 2 | 1 | 9 | 0 | 3 | 4 | 14 | 4 | 13 | 5 | 8
INPUTP | 3 | 22 | 23 | 21
EXPORTS | 1 | 5 | 10
IMPORTS | 1 | 5 | 8
EQ | 21 | 
   use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 = !use_cartemu/cfg_menu & 
	use_cartemu/N4/use_cartemu/N4_D2
	# !a<14> & a<15> & use_cartemu/cfg_menu & a<13>
	# !a<14> & a<15> & a<13> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2
;Imported pterms FB6_9
	# !a<14> & a<15> & use_cartemu/cfg_enable & a<13> & 
	!use_cartemu/N29/use_cartemu/N29_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_menu & use_cartemu/cfg_enable & 
	!use_cartemu/N29/use_cartemu/N29_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_enable & a<13> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2
	# !a<14> & a<15> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & use_cartemu/cfg_enable & a<13> & 
	use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2;
    use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2.EXP  =  
	!use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/oss_bank<0> & 
	!use_cartemu/oss_bank<1>

MACROCELL | 5 | 10 | use_cartemu/N29/use_cartemu/N29_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 4 | 6 | 16 | 5 | 8 | 5 | 15 | 5 | 11
INPUTS | 19 | $OpTx$FX_DC$522  | use_cartemu/N4/use_cartemu/N4_D2  | phi2  | oldos_n  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2  | $OpTx$FX_DC$577  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | a<14>  | a<15>  | a<13>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>  | rw  | a<11>  | a<12>  | use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2.EXP
INPUTMC | 11 | 5 | 17 | 1 | 0 | 3 | 17 | 7 | 15 | 1 | 17 | 1 | 15 | 6 | 7 | 6 | 1 | 6 | 0 | 6 | 2 | 5 | 9
INPUTP | 8 | 33 | 69 | 22 | 23 | 21 | 56 | 18 | 19
EXPORTS | 1 | 5 | 11
IMPORTS | 1 | 5 | 9
EQ | 20 | 
   use_cartemu/N29/use_cartemu/N29_D2 = !$OpTx$FX_DC$522 & 
	!use_cartemu/N4/use_cartemu/N4_D2
;Imported pterms FB6_10
	# 
	!use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2
	# use_cartemu/cfg_mode<0> & !use_cartemu/oss_bank<0> & 
	!use_cartemu/oss_bank<1>;
    use_cartemu/N29/use_cartemu/N29_D2.EXP  =  phi2 & oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & !$OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 & !$OpTx$FX_DC$577 & 
	!ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !a<14> & !a<15> & phi2 & !a<13> & 
	use_freezer/state<1> & !use_freezer/state<2> & !use_freezer/state<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<14> & !a<15> & phi2 & !a<13> & 
	!use_freezer/state<1> & use_freezer/state<2> & !use_freezer/state<0> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2
	# a<14> & a<15> & !rw & !a<11> & phi2 & !a<13> & 
	a<12> & !use_freezer/state<1> & !use_freezer/state<2> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2

MACROCELL | 1 | 14 | use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 3 | 1 | 1 | 16
INPUTS | 6 | use_cartemu/cfg_menu  | use_cartemu/cfg_sram_bank<2>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<2>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_bank<2>
INPUTMC | 6 | 7 | 9 | 1 | 7 | 1 | 0 | 1 | 3 | 2 | 2 | 0 | 9
EQ | 6 | 
   use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 = !use_cartemu/cfg_menu & 
	!use_cartemu/cfg_sram_bank<2> & use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/cfg_bank<2> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/usdx_bank<2> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 1 | 13 | use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 3 | 4 | 1 | 16
INPUTS | 6 | use_cartemu/cfg_menu  | use_cartemu/cfg_sram_bank<3>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<3>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_bank<3>
INPUTMC | 6 | 7 | 9 | 1 | 6 | 1 | 0 | 1 | 2 | 2 | 2 | 0 | 7
EQ | 6 | 
   use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 = !use_cartemu/cfg_menu & 
	!use_cartemu/cfg_sram_bank<3> & use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/cfg_bank<3> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/usdx_bank<3> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 1 | 16 | $OpTx$FX_DC$571
ATTRIBUTES | 133889 | 0
OUTPUTMC | 3 | 5 | 16 | 1 | 16 | 1 | 17
INPUTS | 12 | use_cartemu/cfg_menu  | use_cartemu/cfg_sram_bank<1>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<1>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_bank<1>  | $OpTx$INV$490  | use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2  | use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2  | $OpTx$FX_DC$571  | use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2  | $OpTx$FX_DC$540
INPUTMC | 12 | 7 | 9 | 1 | 8 | 1 | 0 | 1 | 4 | 2 | 2 | 0 | 12 | 7 | 15 | 1 | 14 | 1 | 13 | 1 | 16 | 1 | 12 | 6 | 17
EXPORTS | 1 | 1 | 17
EQ | 10 | 
   $OpTx$FX_DC$571 = !use_cartemu/cfg_menu & 
	!use_cartemu/cfg_sram_bank<1> & use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/cfg_bank<1> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/usdx_bank<1> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;
    $OpTx$FX_DC$571.EXP  =  !$OpTx$INV$490 & 
	!use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 & 
	!use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 & !$OpTx$FX_DC$571 & 
	!use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 & $OpTx$FX_DC$540

MACROCELL | 1 | 12 | use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 3 | 5 | 1 | 16
INPUTS | 6 | use_cartemu/cfg_menu  | use_cartemu/cfg_sram_bank<4>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<4>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_bank<4>
INPUTMC | 6 | 7 | 9 | 1 | 5 | 1 | 0 | 1 | 1 | 2 | 2 | 0 | 6
EQ | 6 | 
   use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 = !use_cartemu/cfg_menu & 
	!use_cartemu/cfg_sram_bank<4> & use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/cfg_bank<4> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# !use_cartemu/cfg_menu & !use_cartemu/usdx_bank<4> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 6 | 17 | $OpTx$FX_DC$540
ATTRIBUTES | 133889 | 0
OUTPUTMC | 2 | 3 | 7 | 1 | 16
INPUTS | 5 | use_cartemu/cfg_sram_bank<5>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<5>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/cfg_bank<5>
INPUTMC | 5 | 6 | 14 | 1 | 0 | 4 | 11 | 2 | 2 | 0 | 5
EQ | 6 | 
   $OpTx$FX_DC$540 = use_cartemu/cfg_sram_bank<5> & 
	use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/cfg_bank<5> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/usdx_bank<5> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 1 | 15 | $OpTx$FX_DC$577
ATTRIBUTES | 133889 | 0
OUTPUTMC | 7 | 5 | 11 | 3 | 14 | 5 | 8 | 3 | 16 | 1 | 17 | 5 | 7 | 5 | 10
INPUTS | 6 | use_cartemu/cfg_menu  | use_cartemu/cfg_bank<6>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/cfg_usdx<0>  | use_cartemu/cfg_usdx<1>
INPUTMC | 6 | 7 | 9 | 2 | 9 | 2 | 2 | 1 | 0 | 7 | 4 | 7 | 3
EQ | 5 | 
   $OpTx$FX_DC$577 = use_cartemu/cfg_menu
	# use_cartemu/cfg_bank<6> & 
	!use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/cfg_usdx<0> & use_cartemu/cfg_usdx<1> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & !use_cartemu/N4/use_cartemu/N4_D2;

MACROCELL | 6 | 7 | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 20 | 5 | 11 | 3 | 14 | 3 | 8 | 3 | 10 | 3 | 11 | 3 | 13 | 5 | 13 | 5 | 14 | 5 | 16 | 3 | 1 | 3 | 4 | 3 | 5 | 3 | 7 | 5 | 8 | 3 | 16 | 5 | 6 | 3 | 3 | 5 | 7 | 5 | 10 | 5 | 17
INPUTS | 5 | a<14>  | ramdisk_enable_n  | a<15>  | use_pia/pia_ddrb<4>  | use_pia/pia_portb<4>
INPUTMC | 2 | 4 | 8 | 4 | 2
INPUTP | 3 | 22 | 36 | 23
EQ | 2 | 
   ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 = a<14> & !ramdisk_enable_n & !a<15> & 
	use_pia/pia_ddrb<4> & !use_pia/pia_portb<4>;

MACROCELL | 3 | 9 | use_freezer/N24/use_freezer/N24_D2
ATTRIBUTES | 133889 | 0
OUTPUTMC | 15 | 3 | 8 | 3 | 10 | 3 | 11 | 3 | 13 | 5 | 12 | 3 | 4 | 5 | 15 | 3 | 1 | 3 | 3 | 3 | 5 | 3 | 6 | 3 | 16 | 3 | 15 | 3 | 0 | 5 | 17
INPUTS | 14 | a<14>  | a<15>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/state<0>  | a<13>  | a<4>  | oldos_n  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | a<9>  | a<8>  | a<10>  | $OpTx$FX_SC$591  | dualpokey_n
INPUTMC | 5 | 6 | 1 | 6 | 0 | 6 | 2 | 3 | 17 | 3 | 0
INPUTP | 9 | 22 | 23 | 21 | 2 | 69 | 15 | 13 | 17 | 57
EXPORTS | 1 | 3 | 8
EQ | 10 | 
   use_freezer/N24/use_freezer/N24_D2 = !a<14> & !a<15> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>
	# !a<14> & !a<15> & !use_freezer/state<1> & 
	use_freezer/state<2> & !use_freezer/state<0>;
    use_freezer/N24/use_freezer/N24_D2.EXP  =  a<14> & a<15> & a<13> & a<4> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<9> & !a<8> & !a<10> & a<4> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$FX_SC$591
	# !a<8> & !a<10> & a<4> & !dualpokey_n & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$FX_SC$591

MACROCELL | 3 | 0 | $OpTx$FX_SC$591
ATTRIBUTES | 133889 | 0
OUTPUTMC | 6 | 3 | 15 | 5 | 13 | 3 | 5 | 3 | 7 | 3 | 9 | 3 | 1
INPUTS | 11 | a<14>  | a<15>  | rw  | a<11>  | a<13>  | a<12>  | use_freezer/state<1>  | use_freezer/state<2>  | use_freezer/rom_bank_2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_freezer/N24/use_freezer/N24_D2
INPUTMC | 5 | 6 | 1 | 6 | 0 | 7 | 11 | 3 | 17 | 3 | 9
INPUTP | 6 | 22 | 23 | 56 | 18 | 21 | 19
EXPORTS | 1 | 3 | 1
EQ | 4 | 
   $OpTx$FX_SC$591 = a<14> & a<15> & !rw & !a<11> & !a<13> & a<12> & 
	!use_freezer/state<1> & !use_freezer/state<2>;
    $OpTx$FX_SC$591.EXP  =  a<13> & use_freezer/rom_bank_2 & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2

MACROCELL | 6 | 16 | $OpTx$FX_DC$608
ATTRIBUTES | 133889 | 0
OUTPUTMC | 1 | 5 | 14
INPUTS | 5 | use_cartemu/cfg_sram_bank<0>  | use_cartemu/N4/use_cartemu/N4_D2  | use_cartemu/usdx_bank<0>  | use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2  | use_cartemu/N29/use_cartemu/N29_D2
INPUTMC | 5 | 6 | 15 | 1 | 0 | 4 | 12 | 2 | 2 | 5 | 10
EQ | 4 | 
   $OpTx$FX_DC$608 = use_cartemu/cfg_sram_bank<0> & 
	use_cartemu/N4/use_cartemu/N4_D2
	# use_cartemu/usdx_bank<0> & 
	use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 & use_cartemu/N29/use_cartemu/N29_D2;

MACROCELL | 3 | 15 | $OpTx$FX_DC$538
ATTRIBUTES | 133889 | 0
OUTPUTMC | 5 | 5 | 14 | 5 | 16 | 3 | 1 | 3 | 4 | 3 | 16
INPUTS | 11 | merged_out_dout_or0000/merged_out_dout_or0000_D2  | $OpTx$FX_SC$591  | a<13>  | a<12>  | use_freezer/N24/use_freezer/N24_D2  | a<14>  | a<15>  | oldos_n  | phi2  | $OpTx$INV$490  | use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2
INPUTMC | 5 | 3 | 17 | 3 | 0 | 3 | 9 | 7 | 15 | 1 | 17
INPUTP | 6 | 21 | 19 | 22 | 23 | 69 | 33
EXPORTS | 1 | 3 | 16
EQ | 9 | 
   $OpTx$FX_DC$538 = merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$FX_SC$591
	# !a<13> & !a<12> & 
	merged_out_dout_or0000/merged_out_dout_or0000_D2 & use_freezer/N24/use_freezer/N24_D2
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2;
    $OpTx$FX_DC$538.EXP  =  a<14> & a<15> & phi2 & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2 & $OpTx$INV$490 & 
	!use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2

MACROCELL | 5 | 6 | N0/N0_TRST
ATTRIBUTES | 133889 | 0
OUTPUTMC | 1 | 7 | 16
INPUTS | 7 | freezer_mem_dout<5>/freezer_mem_dout<5>_D2  | merged_out_dout_or0000/merged_out_dout_or0000_D2  | use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2  | use_cartemu/trig3_disable_atari  | ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2  | $OpTx$BIN_STEP$760  | ram_rom_we_OBUF.EXP
INPUTMC | 7 | 3 | 12 | 3 | 17 | 5 | 9 | 7 | 14 | 6 | 7 | 2 | 17 | 5 | 5
IMPORTS | 1 | 5 | 5
EQ | 22 | 
   N0/N0_TRST = freezer_mem_dout<5>/freezer_mem_dout<5>_D2
	# use_cartemu/trig3_disable_atari & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2
	# !merged_out_dout_or0000/merged_out_dout_or0000_D2 & 
	$OpTx$BIN_STEP$760
;Imported pterms FB6_6
	# a<14> & a<15> & a<13> & !oldos_n & 
	!merged_out_dout_or0000/merged_out_dout_or0000_D2
	# !a<14> & !a<15> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>
	# !a<14> & !a<15> & !use_freezer/state<1> & 
	use_freezer/state<2> & !use_freezer/state<0>
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & !use_freezer/state<1> & 
	use_freezer/state<2>
	# a<14> & a<15> & !a<11> & a<9> & a<8> & a<10> & 
	!a<13> & a<12> & use_freezer/state<1> & 
	!use_freezer/state<2> & !use_freezer/state<0>;

MACROCELL | 2 | 17 | $OpTx$BIN_STEP$760
ATTRIBUTES | 133889 | 0
OUTPUTMC | 1 | 5 | 6
INPUTS | 15 | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | use_cartemu/N97/use_cartemu/N97_D2  | a<14>  | a<15>  | a<12>  | oldos_n  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_mode<0>  | use_cartemu/cfg_mode<1>  | a<7>  | $OpTx$FX_DC$508  | a<3>  | a<0>  | $OpTx$FX_DC$499  | $OpTx$FX_DC$508.EXP
INPUTMC | 8 | 5 | 15 | 2 | 3 | 7 | 6 | 0 | 3 | 7 | 7 | 2 | 0 | 3 | 6 | 2 | 0
INPUTP | 7 | 22 | 23 | 19 | 69 | 11 | 59 | 68
IMPORTS | 1 | 2 | 0
EQ | 25 | 
   $OpTx$BIN_STEP$760 = 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & use_cartemu/N97/use_cartemu/N97_D2
	# a<14> & a<15> & !a<12> & !oldos_n
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# use_cartemu/cfg_mode<2> & !use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
	# a<7> & !a<3> & !a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
;Imported pterms FB3_1
	# !a<1> & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !a<2> & a<7> & !a<3> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# a<6> & !use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2
	# use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	!use_cartemu/cfg_mode<1> & !a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & a<7> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508;

MACROCELL | 0 | 0 | EXP14_
ATTRIBUTES | 2049 | 0
OUTPUTMC | 1 | 0 | 1
INPUTS | 16 | rw  | use_cartemu/cfg_mode<1>  | a<1>  | use_cartemu/cfg_enable  | a<2>  | a<7>  | d<0>.PIN  | a<3>  | reset_n_sync<1>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | $OpTx$FX_DC$508  | use_cartemu/cfg_mode<0>  | a<0>  | use_cartemu/cfg_mode<2>  | use_cartemu/cfg_write_enable.EXP
INPUTMC | 9 | 7 | 7 | 0 | 1 | 6 | 5 | 5 | 15 | 3 | 6 | 2 | 0 | 0 | 3 | 7 | 6 | 0 | 17
INPUTP | 7 | 56 | 79 | 58 | 11 | 24 | 59 | 68
EXPORTS | 1 | 0 | 1
IMPORTS | 1 | 0 | 17
EQ | 28 | 
       EXP14_.EXP  =  !rw & !use_cartemu/cfg_mode<1> & !a<1> & 
	!use_cartemu/cfg_enable & !a<2> & a<7> & d<0>.PIN & !a<3> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & !use_cartemu/cfg_enable & !a<2> & 
	a<7> & d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !rw & !use_cartemu/cfg_mode<0> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<1> & !a<1> & 
	use_cartemu/cfg_enable & !a<2> & a<7> & !d<0>.PIN & !a<3> & a<0> & 
	reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & use_cartemu/cfg_enable & !a<2> & a<7> & 
	!a<3> & !a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508
;Imported pterms FB1_18
	# !rw & use_cartemu/cfg_mode<2> & 
	use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<2> & 
	!use_cartemu/cfg_mode<0> & !a<1> & !use_cartemu/cfg_enable & !a<2> & a<7> & 
	d<0>.PIN & !a<3> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499

MACROCELL | 0 | 16 | EXP15_
ATTRIBUTES | 2049 | 0
OUTPUTMC | 1 | 0 | 17
INPUTS | 15 | rw  | use_cartemu/cfg_mode<2>  | a<1>  | a<2>  | a<7>  | d<0>.PIN  | use_cartemu/cfg_write_enable  | a<3>  | a<0>  | use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2  | $OpTx$FX_DC$499  | use_cartemu/cfg_mode<0>  | reset_n_sync<1>  | $OpTx$FX_DC$508  | use_cartemu/cfg_mode<1>
INPUTMC | 8 | 7 | 6 | 0 | 17 | 5 | 15 | 3 | 6 | 0 | 3 | 6 | 5 | 2 | 0 | 7 | 7
INPUTP | 7 | 56 | 79 | 58 | 11 | 24 | 59 | 68
EXPORTS | 1 | 0 | 17
EQ | 18 | 
       EXP15_.EXP  =  !rw & use_cartemu/cfg_mode<2> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & use_cartemu/cfg_write_enable & !a<3> & 
	a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !use_cartemu/cfg_mode<0> & !a<1> & a<2> & 
	a<7> & !d<0>.PIN & use_cartemu/cfg_write_enable & !a<3> & 
	a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & a<2> & a<7> & d<0>.PIN & 
	!use_cartemu/cfg_write_enable & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499
	# !rw & !a<1> & a<2> & a<7> & !d<0>.PIN & 
	use_cartemu/cfg_write_enable & !a<3> & a<0> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$499 & !$OpTx$FX_DC$508
	# !use_cartemu/cfg_mode<2> & use_cartemu/cfg_mode<0> & 
	use_cartemu/cfg_mode<1> & !a<1> & a<2> & a<7> & 
	!use_cartemu/cfg_write_enable & !a<3> & a<0> & reset_n_sync<1> & 
	use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 & $OpTx$FX_DC$508

MACROCELL | 5 | 4 | EXP16_
ATTRIBUTES | 2049 | 0
OUTPUTMC | 1 | 5 | 5
INPUTS | 2 | rw  | phi2short
INPUTP | 2 | 56 | 42
EXPORTS | 1 | 5 | 5
EQ | 1 | 
       EXP16_.EXP  =  !rw & phi2short

PIN | a<14> | 64 | 0 | N/A | 22 | 30 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6 | 5 | 11 | 3 | 14 | 2 | 17 | 5 | 5 | 3 | 11 | 3 | 13 | 5 | 10 | 3 | 4 | 3 | 6 | 5 | 8 | 3 | 16 | 5 | 14 | 3 | 17 | 3 | 12 | 3 | 3 | 1 | 0 | 5 | 9 | 6 | 7 | 3 | 9 | 3 | 0 | 3 | 15 | 5 | 16
PIN | ramdisk_enable_n | 64 | 0 | N/A | 36 | 1 | 6 | 7
PIN | a<15> | 64 | 0 | N/A | 23 | 31 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6 | 5 | 11 | 3 | 14 | 2 | 17 | 5 | 5 | 3 | 11 | 3 | 13 | 5 | 10 | 3 | 4 | 3 | 6 | 5 | 7 | 3 | 16 | 5 | 14 | 3 | 17 | 3 | 12 | 3 | 3 | 1 | 0 | 5 | 9 | 6 | 7 | 3 | 9 | 3 | 0 | 3 | 15 | 5 | 8 | 5 | 16
PIN | rw | 64 | 0 | N/A | 56 | 55 | 0 | 2 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 2 | 11 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 1 | 10 | 0 | 9 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 12 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 1 | 4 | 11 | 1 | 11 | 7 | 2 | 7 | 10 | 2 | 1 | 2 | 7 | 2 | 4 | 2 | 6 | 5 | 10 | 5 | 7 | 5 | 4 | 3 | 16 | 3 | 17 | 3 | 12 | 0 | 0 | 0 | 4 | 7 | 1 | 1 | 0 | 1 | 17 | 3 | 0 | 0 | 13 | 0 | 16
PIN | a<11> | 64 | 0 | N/A | 18 | 16 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6 | 5 | 10 | 3 | 16 | 3 | 17 | 3 | 12 | 3 | 3 | 3 | 0 | 5 | 5 | 5 | 16
PIN | a<9> | 64 | 0 | N/A | 15 | 19 | 7 | 14 | 7 | 2 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 5 | 5 | 3 | 16 | 3 | 17 | 3 | 12 | 4 | 0 | 3 | 2 | 7 | 1 | 5 | 16 | 4 | 1 | 3 | 9
PIN | a<8> | 64 | 0 | N/A | 13 | 19 | 7 | 14 | 7 | 2 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 5 | 5 | 3 | 16 | 3 | 17 | 3 | 12 | 4 | 0 | 3 | 2 | 7 | 1 | 5 | 16 | 4 | 1 | 3 | 9
PIN | a<10> | 64 | 0 | N/A | 17 | 17 | 7 | 14 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 5 | 5 | 3 | 16 | 3 | 17 | 3 | 12 | 4 | 0 | 3 | 2 | 4 | 1 | 3 | 9 | 5 | 16
PIN | a<6> | 64 | 0 | N/A | 8 | 37 | 2 | 8 | 0 | 14 | 2 | 5 | 2 | 10 | 0 | 15 | 0 | 13 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 2 | 9 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 2 | 1 | 2 | 4 | 2 | 6 | 3 | 11 | 3 | 12 | 7 | 17 | 3 | 6 | 2 | 3 | 2 | 7 | 0 | 4 | 4 | 1 | 2 | 0 | 7 | 0
PIN | a<5> | 64 | 0 | N/A | 6 | 25 | 2 | 8 | 0 | 14 | 2 | 5 | 2 | 10 | 0 | 15 | 0 | 5 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 4 | 15 | 7 | 10 | 2 | 1 | 2 | 4 | 2 | 6 | 3 | 10 | 3 | 12 | 7 | 17 | 3 | 6 | 2 | 3 | 0 | 13 | 2 | 7 | 3 | 11 | 7 | 0
PIN | a<7> | 64 | 0 | N/A | 11 | 39 | 0 | 2 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 14 | 4 | 13 | 3 | 13 | 3 | 12 | 2 | 3 | 0 | 0 | 0 | 4 | 3 | 3 | 3 | 2 | 2 | 17 | 0 | 8 | 0 | 16 | 2 | 0 | 2 | 7
PIN | a<3> | 64 | 0 | N/A | 59 | 43 | 0 | 2 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 0 | 9 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 14 | 7 | 2 | 2 | 13 | 4 | 17 | 2 | 1 | 2 | 4 | 2 | 6 | 3 | 12 | 2 | 3 | 0 | 0 | 0 | 4 | 7 | 1 | 2 | 7 | 2 | 17 | 0 | 13 | 0 | 16 | 2 | 0
PIN | a<2> | 64 | 0 | N/A | 58 | 38 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 8 | 0 | 8 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 7 | 2 | 2 | 14 | 7 | 11 | 2 | 1 | 7 | 17 | 2 | 3 | 0 | 0 | 0 | 4 | 7 | 1 | 2 | 0 | 2 | 7 | 0 | 2 | 0 | 13 | 0 | 16 | 7 | 0
PIN | a<1> | 64 | 0 | N/A | 79 | 39 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 0 | 9 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 7 | 2 | 2 | 15 | 7 | 12 | 7 | 17 | 2 | 3 | 0 | 0 | 0 | 4 | 7 | 1 | 2 | 0 | 2 | 7 | 0 | 2 | 0 | 13 | 0 | 16 | 7 | 0
PIN | a<0> | 64 | 0 | N/A | 68 | 44 | 2 | 8 | 0 | 10 | 0 | 11 | 0 | 14 | 2 | 5 | 2 | 10 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 15 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 0 | 13 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 7 | 14 | 2 | 9 | 7 | 5 | 0 | 17 | 4 | 13 | 7 | 2 | 2 | 16 | 7 | 13 | 2 | 1 | 2 | 4 | 2 | 6 | 3 | 12 | 7 | 17 | 2 | 3 | 0 | 0 | 0 | 4 | 7 | 1 | 2 | 7 | 2 | 17 | 0 | 2 | 0 | 9 | 0 | 16 | 7 | 0
PIN | a<4> | 64 | 0 | N/A | 2 | 21 | 2 | 8 | 0 | 14 | 2 | 5 | 2 | 10 | 0 | 15 | 0 | 6 | 2 | 12 | 4 | 16 | 2 | 1 | 2 | 4 | 2 | 6 | 3 | 8 | 3 | 12 | 7 | 17 | 3 | 6 | 2 | 3 | 0 | 13 | 4 | 1 | 2 | 7 | 3 | 9 | 7 | 0
PIN | phi2short | 16448 | 0 | N/A | 42 | 63 | 5 | 4 | 7 | 6 | 0 | 3 | 7 | 7 | 7 | 9 | 0 | 1 | 7 | 4 | 7 | 3 | 7 | 8 | 1 | 10 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 7 | 0 | 6 | 0 | 5 | 2 | 9 | 7 | 5 | 6 | 15 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 6 | 14 | 0 | 17 | 4 | 14 | 4 | 13 | 4 | 12 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 1 | 4 | 11 | 1 | 11 | 7 | 2 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 7 | 13 | 7 | 12 | 7 | 11 | 4 | 17 | 4 | 16 | 4 | 15 | 7 | 10 | 2 | 1 | 4 | 10 | 4 | 9 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 4 | 4 | 3 | 4 | 2 | 6 | 13 | 6 | 12 | 6 | 11 | 2 | 7 | 2 | 4 | 2 | 6
PIN | cartemu_enable_n | 64 | 0 | N/A | 12 | 2 | 7 | 9 | 5 | 16
PIN | phi2 | 4160 | 0 | N/A | 33 | 19 | 0 | 15 | 5 | 11 | 3 | 14 | 5 | 7 | 5 | 8 | 3 | 16 | 0 | 14 | 3 | 15 | 5 | 10 | 6 | 8 | 6 | 5 | 6 | 1 | 6 | 0 | 6 | 2 | 6 | 9 | 6 | 4 | 6 | 10 | 6 | 6 | 6 | 3
PIN | a<13> | 64 | 0 | N/A | 21 | 36 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6 | 5 | 11 | 3 | 14 | 3 | 8 | 3 | 10 | 3 | 11 | 3 | 13 | 5 | 12 | 5 | 14 | 5 | 15 | 3 | 1 | 5 | 5 | 3 | 5 | 3 | 6 | 5 | 7 | 3 | 16 | 5 | 10 | 3 | 17 | 3 | 12 | 3 | 3 | 1 | 0 | 5 | 9 | 3 | 0 | 3 | 15 | 3 | 4 | 3 | 9 | 5 | 8 | 5 | 16 | 5 | 17
PIN | a<12> | 64 | 0 | N/A | 19 | 22 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 1 | 2 | 4 | 2 | 6 | 5 | 10 | 5 | 13 | 5 | 12 | 5 | 14 | 3 | 17 | 3 | 12 | 3 | 3 | 3 | 0 | 3 | 15 | 5 | 5 | 2 | 17 | 3 | 16 | 5 | 15 | 5 | 16
PIN | flash_we_n | 64 | 0 | N/A | 29 | 2 | 1 | 17 | 5 | 16
PIN | oldos_n | 64 | 0 | N/A | 69 | 13 | 5 | 10 | 3 | 14 | 2 | 17 | 3 | 9 | 3 | 11 | 3 | 13 | 5 | 5 | 3 | 4 | 3 | 6 | 5 | 7 | 3 | 16 | 3 | 15 | 5 | 14
PIN | dualpokey_n | 64 | 0 | N/A | 57 | 2 | 3 | 10 | 3 | 9
PIN | activate_n_in | 64 | 0 | N/A | 72 | 1 | 6 | 10
PIN | reset_n_in | 64 | 0 | N/A | 160 | 1 | 6 | 6
PIN | extsel_in | 64 | 0 | N/A | 4 | 0
PIN | irq_in | 64 | 0 | N/A | 77 | 0
PIN | mpd_in | 64 | 0 | N/A | 35 | 0
PIN | nc_adr<1> | 64 | 0 | N/A | 114 | 0
PIN | nc_adr<2> | 64 | 0 | N/A | 116 | 0
PIN | nc_adr<3> | 64 | 0 | N/A | 118 | 0
PIN | nc_adr<4> | 64 | 0 | N/A | 123 | 0
PIN | ram0_ce | 128 | 0 | N/A | 135
PIN | ram1_ce | 128 | 0 | N/A | 155
PIN | ram_a<4> | 128 | 0 | N/A | 146
PIN | ram_a<5> | 128 | 0 | N/A | 147
PIN | ram_a<6> | 128 | 0 | N/A | 149
PIN | ram_a<7> | 128 | 0 | N/A | 153
PIN | ram_rom_a<12> | 128 | 0 | N/A | 136
PIN | ram_rom_a<13> | 128 | 0 | N/A | 139
PIN | ram_rom_a<14> | 128 | 0 | N/A | 140
PIN | ram_rom_a<15> | 128 | 0 | N/A | 141
PIN | ram_rom_a<16> | 128 | 0 | N/A | 143
PIN | ram_rom_a<17> | 128 | 0 | N/A | 144
PIN | ram_rom_a<18> | 128 | 0 | N/A | 145
PIN | ram_rom_oe | 128 | 0 | N/A | 127
PIN | ram_rom_we | 128 | 0 | N/A | 125
PIN | rom0_ce | 128 | 0 | N/A | 130
PIN | rom1_ce | 128 | 0 | N/A | 157
PIN | refresh | 128 | 0 | N/A | 117
PIN | d<0> | 64 | 0 | N/A | 24 | 10 | 0 | 3 | 0 | 0 | 7 | 4 | 7 | 8 | 0 | 12 | 6 | 15 | 0 | 17 | 4 | 12 | 0 | 2 | 0 | 16
PIN | d<5> | 64 | 0 | N/A | 44 | 5 | 0 | 5 | 6 | 14 | 4 | 11 | 4 | 7 | 6 | 13
PIN | d<1> | 64 | 0 | N/A | 26 | 6 | 7 | 7 | 7 | 3 | 0 | 12 | 7 | 5 | 1 | 8 | 1 | 4
PIN | d<2> | 64 | 0 | N/A | 28 | 8 | 7 | 6 | 7 | 9 | 0 | 8 | 1 | 7 | 1 | 3 | 7 | 2 | 4 | 10 | 4 | 4
PIN | d<3> | 64 | 0 | N/A | 30 | 5 | 0 | 7 | 1 | 6 | 1 | 2 | 4 | 9 | 4 | 3
PIN | d<4> | 64 | 0 | N/A | 37 | 5 | 0 | 6 | 1 | 5 | 1 | 1 | 4 | 8 | 4 | 2
PIN | d<6> | 64 | 0 | N/A | 47 | 4 | 2 | 9 | 1 | 11 | 4 | 6 | 6 | 12
PIN | d<7> | 64 | 0 | N/A | 49 | 3 | 1 | 10 | 4 | 5 | 6 | 11
